Mitsubishi Denki Kabushiki Kaisha

Renesas Electronics Corporation

Renesas Technology Corp.

Kengo Aritomi

Takashi Kubo

Tadaaki Yamauchi

Taku Ogura

Hidenori Mitani

Mikio Asakura

Kiyohiro Furutani

Takashi Ito

Yasuhiko Tsukikawa

Takashi Itou

Takayuki Miyamoto

A semiconductor device includes a semiconductor substrate having first and second edge lines, address pads along the first edge line, and memory mats, each including normal memory blocks and a spare memory block. Each normal memory block has nonvolatile memory cells and is a unit of batch erase. The memory mats are arranged in a U-shaped area having a hollow portion facing the second edge line. The device includes column decoders arranged correspondingly to the memory mats, an analog/logic circuit arranged in the hollow portion, and a power supply pad arranged between the analog/logic circuit and the second edge line. The analog/logic circuit includes a charge pump circuit. The device further includes a first power supply interconnection supplying power supply voltage to the charge pump circuit from the power supply pad, and a second power supply interconnection supplying power supply voltage to the column decoder from the power supply pad.

Semiconductor memory device having memory block configuration

A memory apparatus includes a control circuit, a plurality of memory arrays, each of which contains a plurality of memory cells, and a current detecting circuit. The current detecting circuit measures a quantity of a current of a first memory array. A redundancy information is changed when the quantity of the current of the first memory array is over a first current quantity detected by the current detecting circuit. The control circuit controls an access to the memory arrays, and changes the access to the first memory array to a second memory array in accordance with the redundancy information.

A memory array including memory mats is arranged in a U shape when seen in two dimensions, and a logic circuit and an analog circuit are arranged in a region unoccupied by the memory array. This facilitates transmission of power supply voltage and signals between the peripheral circuit including the analog and logic circuits and the pad band including power supply and data pads. The analog circuit is positioned close to the power supply pad, so that voltage drop due to the resistance of power supply interconnection is restricted. It is also possible to separate a charge pumping power supply interconnection and a peripheral circuit power supply interconnection in the vicinity of the power supply pad.

In generating sub decode signals for specifying a sub word line in a hierarchical word line structure, a first sub decode signal transmitted to a selected sub word line is generated from a sub decode first signal, and a second sub decode signal for holding a non-selected sub word line at a non-selected state is generated by a gate circuit receiving the first sub decode signal and the signal generated on the basis of the sub decode first signal. When the first sub decode signal is selected, the logic level of the second sub decode signal can be changed at high speed. Consequently, a period in which a path through which a through-current flows in a sub word driver can be made sufficiently short and accordingly, the current consumption can be reduced.

Semiconductor memory device having hierarchical word line structure

A semiconductor memory device includes a plurality of array blocks including word lines, memory cells, bit lines, dummy word lines and transistors. In a test mode, rather than a word line a dummy word line is selected. Selectively turning on either one of the transistors allows a bit line connected thereto to be driven to a ground potential. Thus, a channel leak can be detected. In a mode other than the test mode, a defective word line is substituted by a spare word line included in a spare block.

Semiconductor memory device with memory test circuit

Complementary sub-decode signals to be provided to a sub-word line driver are separately generated through different circuits using individual power-supply voltages. Thus, the generation of a through current in the sub-word line driver is prevented.

Semiconductor memory device with a hierarchical word line configuration capable of preventing leakage current in a sub-word line driver

A semiconductor integrated circuit device includes a plurality of data input/output terminals to transmit send/receive a plurality of input/output data signals to/from an external source, a mode set circuit to set an operation mode of the semiconductor integrated circuit device and generating a plurality of capacitance set signals according to a combination of externally applied control signals, and a plurality of variable capacitance circuits respectively provided between a predetermined reference potential and a plurality of data input/output terminals, capable of changing independently the capacitance according to a capacitance set signal.

Semiconductor integrated circuit device that can suppress generation of signal skew between data input/output terminals

There is provided a test mode decision circuit which in the first WCBR cycle responds to an address key by activating a test mode entry signal and with the test mode entry signal activated in the second WCBR cycle responds to an address key by selectively activating test mode signals. In addition to a test mode signal having been activated, the test mode decision circuit further activates another test mode signal. Thus the DRAM hardly enter a test mode erroneously and is also capable of entering more than one test mode simultaneously.

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Hyogo, Japan

Kengo Aritomi