Taiwan Semiconductor Manufacturing Comp. Ltd.

Keng-Yao Chen

Chang-Yun Chang

Ming-Chang Wen

Yi-Ting Fu

Chen-Yu Tai

The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate and a second metal gate stack in an active device region of the semiconductor substrate, and performing a chemical mechanical polishing (CMP) process using a slurry including charged abrasive nanoparticles. The first and second metal gate stacks are different in composition. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region.

Local gate height tuning by CMP and dummy gate design

The embodiments described herein are directed to a method for mitigating the fringing capacitances generated by patterned gate structures. The method includes forming a gate structure on fin structures disposed on a substrate; forming an opening in the gate structure to divide the gate structure into a first section and a second section, where the first and second sections are spaced apart by the opening. The method also includes forming a fill structure in the opening, where forming the fill structure includes depositing a silicon nitride liner in the opening to cover sidewall surfaces of the opening and depositing silicon oxide on the silicon nitride liner.

Structure for fringing capacitance control

The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height different from a second height of the second metal gate stack.

Local gate height tuning by cmp and dummy gate design

The present disclosure describes fabricating devices with tunable gate height and effective capacitance. A method includes forming a first metal gate stack in a dummy region of a semiconductor substrate, the first metal gate stack including a first work function metal (WFM) layer; forming a second metal gate stack in an active device region of the semiconductor substrate, the second metal gate stack including a second WFM layer different than the first WFM layer; and performing a CMP process using a slurry including a charged abrasive nanoparticles. The charged abrasive nanoparticles include a first concentration in the active device region different from a second concentration in the dummy region causing different polish rates in the active device region and dummy region. After the performing of the CMP process, the first metal gate stack has a first height greater different from a second height of the second metal gate stack.

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Hsinchu, Taiwan

Keng-Yao Chen