Taiwan Semiconductor Manufacturing Comp. Ltd.

Keng-Hui Liao

Ying-Chen Chao

Chin-Yuan Ko

Yao-Jen Tsai

Sen-Shan Yang

Wi William Lee

Chia-Jen Leu

Chih-kai Yang

Chih-fu Chang

A method includes providing a substrate of a first conductivity type, the substrate including a first circuit region and a second circuit region; forming a first well region of a second conductivity type in the first circuit region of the substrate; forming a first doped region of the second conductivity type in the first well region; forming a diode in the second circuit region of the substrate; forming a first transistor and a second transistor over the substrate in the first circuit region and the second circuit region, respectively; forming a discharge structure over the substrate to electrically couple the first doped region to the diode; and forming a metallization layer over the discharge structure to electrically couple the first transistor to the second transistor subsequent to the forming of the diode, wherein charges accumulated in the first well region are drained to the substrate through the discharge structure.

Semiconductor structure including discharge structures and method for fabricating the same

An accelerated thermal stress cycle test which can be conducted in a significantly reduced test time compared to the conventional test is provided. The test is carried out in a cluster of reaction chambers that includes a CVD chamber and a cool-down chamber such that a pre-processed wafer can be heated from room temperature to at least 350&deg; C. in an inert gas in about 2 min., and then cooled down to not higher than 70&deg; C. in a cool-down chamber in less than 30 sec. The heating and cooling steps can be repeated between 3 and 7 times to reveal any defect formation caused by the thermal stress cycle test. Typical defects are metal film peeling from insulating dielectric material layer or void formation.

Accelerated thermal stress cycle test

Growing community of inventors

Peng-Tung County, Taiwan

Keng-Hui Liao