Taiwan Semiconductor Manufacturing Comp. Ltd.

Vanguard International Semiconductor Corporation

Other

Keng-Chu Lin

Yu-Yun Peng

Shuen-Shin Liang

Sung-Li Wang

Joung-Wei Liou

Mrunal Abhijith Khaderbad

Chung-Chi Ko

Chia-Hung Chu

Shwang-Ming Jeng

Fu-Ting Yen

Ting-Ting Chen

Hsu-Kai Chang

Chia-Cheng Chou

Chen-Han Wang

Tien-I Bao

Tsu-Hsiu Perng

Tetsuji Ueno

Hung-Yi Huang

Pang-Yen Tsai

Hui-Chun Yang

Chen-Hua Douglas Yu

Teng-Chun Tsai

Pinyen Lin

Shing-Chyang Pan

Chih-Wei Chang

Chih-Hao Chen

Chun-Hsien Huang

Ken-Yu Chang

Chun-I Tsai

Chih-Hao Wang

Chin-Hsiang Lin

Kuo-Cheng Ching

Huicheng Chang

Yung-Cheng Lu

Shi-Ning Ju

Cheng-Han Wu

Ya Hui Chang

Tzer-Min Shen

Han-Ti Hsiaw

Mei-Ling Chen

De-Yang Chiou

Kuan-Lun Cheng

Ziwei Fang

Po-Cheng Shih

Hsueh Wen Tsau

Ding-Kang Shih

Fang-Wei Lee

Dhanyakumar Mahaveer Sathaiya

Tsungyu Hung

Wen-Chih Chiou

Syun-Ming Jang Jang

Li-Te S Lin

Ming-Chung Liang

Victor Y Lu

Chih-Tsung Lee

Han-Yu Lin

Yahru Cheng

Tsai-Jung Ho

Jung-Hao Chang

Chia Cheng Chou

Chih-Lung Lin

Hui-Lin Chang

Chien Chang

Wen-Cheng Yang

Yen-Tien Tung

Tzu-Li Lee

Kuan-Cheng Wang

Ya-Ling Lee

Jhih-Rong Huang

Chun-Hao Hsu

Tsung-Han Ko

Chung-Shi Liu

Yasutoshi Okuno

Pei-Ren Jeng

Hung-Wen Su

Liang-Gi Yao

Kuang-Yuan Hsu

Chih-Tang Peng

Tai-Yen Peng

Chih-Chien Chi

Chin-Szu Lee

Cheng-Wei Chang

Kuan-lun Cheng

Zhen-Cheng Wu

Bo-Yu Lai

Hsin-Yi Tsai

Szu-Hua Wu

Yi-Wen Chen

Yi-Ying Liu

Chih-Ta Wu

Chien-Feng Lin

Winnie Victoria Wei-Ning Chen

Chien-Shun Liao

Lih-Ping Li

Wen-Kuo Hsieh

Ching-Ya Wang

Rong-Wu Chien

Pi-Tsung Chen

Ting-Yu Shen

Chia-I Shen

A post-deposition treatment can be applied to an atomic layer deposition (ALD)-deposited film to seal one or more seams at the surface. The seam-top treatment can physically merge the two sides of the seam, so that the surface behaves as a continuous material to allow etching at a substantially uniform rate across the surface of the film. The seam-top treatment can be used to merge seams in ALD-deposited films within semiconductor structures, such as gate-all-around field effect transistors (GAAFETs).

Seam-top seal for dielectrics

The structure of a semiconductor device with source/drain contact structures and via structures and a method of fabricating the semiconductor device are disclosed. A method for fabricating a semiconductor device includes forming a source/drain (S/D) region on a substrate, forming a S/D contact structure on the S/D region, and forming a via structure on the S/D contact structure. The forming of the via structure includes forming a via opening on the S/D contact structure, forming a non-metal passivation layer on sidewalls of the via opening, and depositing a via plug within the via opening in a bottom-up deposition process.

Contact and via structures for semiconductor devices

The present disclosure relates to a method for forming a semiconductor device includes forming an opening between first and second sidewalls of respective first and second terminals. The first and second sidewalls oppose each other. The method further includes depositing a first dielectric material at a first deposition rate on top portions of the opening and depositing a second dielectric material at a second deposition rate on the first dielectric material and on the first and second sidewalls. The second dielectric material and the first and second sidewalls entrap a pocket of air. The method also includes performing a treatment process on the second dielectric material.

Bilayer seal material for air gaps in semiconductor devices

The present disclosure describes a method for forming liner-free or barrier-free conductive structures. The method includes depositing an etch stop layer on a cobalt contact disposed on a substrate, depositing a dielectric on the etch stop layer, etching the dielectric and the etch stop layer to form an opening that exposes a top surface of the cobalt contact, and etching the exposed top surface of the cobalt contact to form a recess in the cobalt contact extending laterally under the etch stop layer. The method further includes depositing a ruthenium metal to substantially fill the recess and the opening, and annealing the ruthenium metal to form an oxide layer between the ruthenium metal and the dielectric.

Liner-free conductive structures with anchor points

An integrated circuit (IC) device includes a semiconductor substrate having a first plurality of stacked semiconductor layers in a p-type transistor region and a second plurality of stacked semiconductor layers in a n-type transistor region. A gate dielectric layer wraps around each of the first and second plurality of stacked semiconductor layers. A first metal gate in the p-type transistor region has a work function metal layer and a first fill metal layer, where the work function metal layer wraps around and is in direct contact with the gate dielectric layer and the first fill metal layer is in direct contact with the work function metal layer. A second metal gate in the n-type transistor region has a second fill metal layer that is in direct contact with the gate dielectric layer, where the second fill metal layer has a work function about equal to or lower than 4.3 eV.

Low resistance fill metal layer material as stressor in metal gates

A semiconductor device includes a semiconductor substrate, a channel region, a gate structure, two epitaxial structures, and two silicide structures. The channel region is disposed on the semiconductor substrate. The gate structure is disposed on the semiconductor substrate and over the channel region. The epitaxial structures are connected at opposite ends of the channel region and are disposed opposite to each other relative to the gate structure. The silicide structures respectively surround the epitaxial structures. A method of manufacturing a semiconductor device is also provided.

Semiconductor device with silicide structures surrounding epitaxial structures and method of making the same

A method for manufacturing a semiconductor device includes: forming a patterned mask on a patterned structure disposed on a substrate, such that a first mask portion and a second mask portion of the patterned mask are disposed on a first interconnect feature and a second interconnect feature of the patterned structure, respectively; and subjecting the patterned mask to a plasma treatment process such that the first and second mask portions are deformed to form a capping portion to cap a recess disposed between the first and second interconnect features so as to form an air gap.

Semiconductor device having air gap and method for manufacturing the same

The present disclosure describes a method of fabricating a semiconductor structure that includes forming a fin structure on a substrate, forming a polysilicon gate structure on a first portion of the fin structure, forming an opening in a second portion of the fin structure, wherein the first and second portions of the fin structure is adjacent to each other, forming a recess laterally on a sidewall of the first portion of the fin structure underlying the polysilicon gate structure, and forming an inner spacer structure within the recess. The inner spacer structure comprises an inner air spacer enclosed by a first dielectric spacer layer and a second dielectric spacer layer.

Semiconductor devices with tunable low-K inner air spacers

The present disclosure describes a semiconductor structure and a method for forming the same. The semiconductor structure can include a substrate, a gate structure over the substrate, a source/drain (S/D) contact structure adjacent to the gate structure, a layer of dielectric material over the S/D contact structure and over the gate structure, a layer of organometallic material formed through the layer of dielectric material, and a trench conductor layer formed through the layer of dielectric material and in contact with the S/D contact structure and the gate structure. The layer of organometallic material can be between the layer of dielectric material and the trench conductor layer.

Contact structure for semiconductor device

A semiconductor device with densified dielectric structures and a method of fabricating the same are disclosed. The method includes forming a fin structure, forming an isolation structure adjacent to the fin structure, forming a source/drain (S/D) region on the fin structure, depositing a flowable dielectric layer on the isolation structure, converting the flowable dielectric layer into a non-flowable dielectric layer, performing a densification process on the non-flowable dielectric layer, and repeating the depositing, converting, and performing to form a stack of densified dielectric layers surrounding the S/D region.

Dielectric structures in semiconductor devices

A semiconductor structure includes a semiconductor fin, a doped dielectric fin, a shallow trench isolation (STI) oxide, a gate structure, and source/drain regions. The semiconductor fin upwardly extends from a substrate. The doped dielectric fin upwardly extends above the substrate. The doped dielectric fin is implanted with an impurity therein. The STI oxide laterally surrounds a lower portion of the semiconductor fin and a lower portion of the doped dielectric fin. The gate structure extends across the semiconductor fin and the doped dielectric fin. The source/drain regions are on the semiconductor fin and at opposite sides of the gate structure.

Semiconductor device and manufacturing method thereof

The present disclosure describes a method to form a bonded semiconductor structure. The method includes forming a first bonding layer on a first wafer, forming a debonding structure on a second wafer, forming a second bonding layer on the debonding structure, bonding the first and second wafers with the first and second bonding layers, and debonding the second wafer from the first wafer via the debonding structure. The debonding structure includes a first barrier layer, a second barrier layer, and a water-containing dielectric layer between the first and second barrier layers.

Debonding structures for wafer bonding

A method includes receiving a structure having a dielectric layer over a conductive feature, wherein the conductive feature includes a second metal. The method further includes etching a hole through the dielectric layer and exposing the conductive feature and depositing a first metal into the hole and in direct contact with the dielectric layer and the conductive feature, wherein the first metal entirely fills the hole. The method further includes annealing the structure such that atoms of the second metal are diffused into grain boundaries of the first metal and into interfaces between the first metal and the dielectric layer. After the annealing, the method further includes performing a chemical mechanical planarization (CMP) process to remove at least a portion of the first metal.

Method and structure for barrier-less plug

Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first semiconductor channel member and a second semiconductor channel member over the first semiconductor channel member and a porous dielectric feature that includes silicon and nitrogen. In the semiconductor device, the porous dielectric feature is sandwiched between the first and second semiconductor channel members and a density of the porous dielectric feature is smaller than a density of silicon nitride.

Inner spacers for gate-all-around semiconductor devices

The present disclosure describes a semiconductor device and methods for forming the same. The semiconductor device includes a first transistor device of a first type and a second transistor device of a second type. The first transistor device includes first nanostructures, a first pair of source/drain structures, and a first gate structure on the first nanostructures. The second transistor device of a second type is formed over the first transistor device. The second transistor device includes second nanostructures over the first nanostructures, a second pair of source/drain structures over the first pair of source/drain structures, and a second gate structure on the second nanostructures and over the first nanostructures. The semiconductor device further includes a first isolation structure in contact with the first and second nanostructures and a second isolation structure in contact with a top surface of the first pair of source/drain structures.

Gate structures for stacked semiconductor devices

Growing community of inventors

Ping-Tung, Taiwan

Keng-Chu Lin