Cypress Semiconductor Corporation

Kenelm G Murray

Donato Montanari

Andrew J Walker

Brenor L Brophy

Morgan Andrew Whately

Mark W Rouse

The present invention provides a programmable on-chip resistance. An apparatus of the present invention may utilize an analog scheme and adjusts the termination resistance in real-time. One way of implementing the invention is the use of a single transistor with analog control that may vary the resistance for differential input ports. This may provide a reduction in parasitic capacitance as viewed by a high-speed driver while reducing the requirement of over-driving the gate to reduce the impedance of the transistor.

Architecture for programmable on-chip termination

The present invention is a method and apparatus for producing a programmable on-chip resistance. A programmable on-chip resistance is maintained to provide a constant resistance for differential input common mode voltage changes and may provide a constant resistance over changes in an amplitude of an input differential swing. The programmable on-chip resistance may be implemented through a single transistor in which a control voltage for altering the resistance of the transistor is produced by the use of an intermediate termination device. The intermediate termination device may replicate the programmable on-chip termination device to ensure proper adjustment of the on-chip termination device to maintain a constant resistance.

Programmable on-chip termination device

A semiconductor device includes a grounded-gate n-channel field effect transistor (FET) between an I/O pad and ground (V ) and/or V for providing ESD protection. The FET includes a tap region of grounded p-type semiconductor material in the vicinity of the n -type source region of the FET, which is also tied to ground, to make the ESD protection device less sensitive to substrate noise. The p-type tap region comprises either (i) a plurality of generally bar shaped subregions disposed in parallel relation to n source subregions, or, (ii) a region that is generally annular in shape and surrounds the n&plus; source region. The p-type tap region functions to inhibit or prevent snapback of the ESD device, particularly inadvertent conduction of a parasitic lateral npn bipolar transistor, resulting from substrate noise during programming operations on an EPROM device or in general used in situations where high voltages close to but lower than the snapback voltage are required in the pin.

ESD structure having an improved noise immunity in CMOS and BICMOS semiconductor devices

According to one embodiment, a nonvolatile circuit ( ) can include a volatile circuit portion ( ) and a nonvolatile circuit portion ( ). A vole portion ( ) may have a first data node ( ) and a second data node ( ). A nonvolatile circuit portion ( ) may include a nonvolatile device ( ) that is connected to a first data node ( ) by a recall device ( ) and connected to a second data node ( ) by store device ( ). A recall device ( ) may be enabled to recall the volatile circuit portion ( ) to a particular state. A store device ( ) may be enabled to program a nonvolatile device ( ). Store and recall devices ( and ) can enable a recall operation to follow a store operation that does not invert data at first and second data nodes ( and ). A control device ( ) can be included that enables margin testing of a nonvolatile device ( ).

Compact nonvolatile circuit having margin testing capability

A circuit comprising a positive switch and a steering network. The positive switch may be configured to present a first and a second switch signal in response to a first select signal. The steering network may be configured to present a high voltage output that may transition between a very high positive and a very low negative voltage, where the transition may respond to a high positive voltage input, a low negative voltage input, a first and second switch signal, and a second select signal.

High voltage steering network for EEPROM/FLASH memory

A high voltage switch for use in an EEPROM/FLASH memory that may be implemented using a twin-well process (e.g., using only P-channel transistors). The circuit comprises a positive switch configured to present a first and a second switch signal in response to (i) one or more select signals and (ii) an address signal and a second switch configured to present a programing voltage in response to (i) the select signals, (ii) the first and second switch signals and (iii) a high voltage source. A high voltage positive and negative pump may provide the high voltage source.

High voltage switch for eeprom/flash memories

A two-transistor, zero DC power, non-volatile inverter latch that can be made using floating-gate or SONOS technology to provide a consistent and/or reliable logic high and/or logic low output level. The inventive cell is useful for holding option settings in any custom integrated circuit or, more specifically, for holding configuration information (e.g., ASIC, PLD or FPGA interconnect data; configuration data for such ICs or for a clock/oscillator circuit or a microcontroller, etc.). The inventive cell outputs the data state immediately on power-up without any need for recall sequencing. The benefit of the invention comes from the potential for a very small cell which, in many applications, can substitute for non-volatile RAM.

Non-volatile inverter latch

A method and apparatus comprising a first circuit configured to generate a first output in response to a first input, a second circuit configured to present a second output in response to a second input, and a third circuit configured to generate a first voltage signal and a second voltage signal in response to the first output and said second output. The first voltage signal may be above the positive supply and the second voltage signal may be below the negative supply.

Growing community of inventors

Sunnyvale, CA, United States of America

Kenelm G Murray