Advanced Micro Devices Corporation

Other

Spansion Llc.

Exar Corporation

Kendra Nguyen

Lee Edward Cleveland

Takao Akaogi

Ali K Al-Shamma

Yong K Kim

Jin-Lien Lin

Boon Tang Teh

Yong Bae Kim

Darlene G Hamilton

Xin Sheng Guo

Dimitry Goder

Ken Cheong Cheah

Mimi Lee

Zongqi Hu

A switching voltage regulator includes, in part, N output stages, a loop ADC, a multiplexer, a current ADC, and an interrupt block. The loop analog-to-digital converter receives the N output voltages each of which is associated with one of N channels. The loop ADC is adapted to vary a duty cycle of N signals each applied to one of the N output stages that generate the N output voltages. The interrupt block is adapted to enable the multiplexer to couple an output stage to the current ADC if a difference between voltages sensed at an output stage during at least two sampling times exceeds a predefined threshold value. The interrupt block may also be adapted to enable the multiplexer to couple an output stage to the current ADC block if a difference between a voltage sensed at the output stage and a reference voltage exceeds a predefined threshold value.

Interrupt based multiplexed current limit circuit

A method is discussed for providing programmable test conditions for a built-in self test circuit of a flash memory device. The method comprises providing a BIST interface adapted to adjust a test condition used in a BIST circuit, providing the memory cells of the Flash memory device, and providing the BIST circuit adapted to test the flash memory. The method further comprises communicating with the BIST interface one or more global variables associated with the test condition, adjusting the test condition used by the BIST circuit based on the values represented by the global variables, performing one or more test operations on the flash memory in accordance with the adjusted test condition, and reporting the results of the memory test operations. The method of the present invention may further include a serial communications medium and the use of a serial test protocol for communicating the global variables to the BIST interface and test results from the interface. The global variables may also be provided by a memory device user.

Automated tests for built-in self test

A method for operating a flash memory includes, in response to a received operation command, initiating an embedded operation of the flash memory and subsequently, during execution of the embedded operation, in response to a received read command, initiating a burst read operation of the flash memory.

Simultaneous execution command modes in a flash memory device

A burst mode architecture to provide burst mode access to a plurality of data words in a flash memory is described. The burst mode architecture includes a first circuit, a control circuit coupled to the first circuit, and a data buffer selectively coupled to the first circuit by the control circuit. The first circuit accesses a plurality of data words, beginning with an initial access of a first data word and a second data word. The control circuit generates a timing signal having pulses and a second signal. The second signal is generated upon completion of the initial access of the first data word and the second data word. The first circuit follows the initial access with subsequent accesses of the plurality of data words responsively to the second signal and the timing signal. The data buffer has an output and produces the first data word at the output and successively produces, with each successive pulse of the timing signal following an initial period of time, the second data word, and subsequent data words at the output. The subsequent data words correspond to the subsequent accesses of the plurality of data words.

Burst architecture for a flash memory

A method of charging a data line to a desired voltage level prior to the data line being sensed in a low power memory device by discharging the data line from a voltage level above the desired voltage level to approximately the desired voltage level. By using N-type transistors to discharge the data line to the desired voltage level, the voltage level can be reached faster with cheaper components.

Memory line discharge before sensing

A non-volatile semiconductor memory device comprising a memory array, the memory array divided into a plurality of sectors, each sector comprising a plurality of memory cells, which can be electrically erased, and an erase-verify circuit, capable of simultaneously erasing multiple memory sectors. The erase-verify circuit simultaneously erases a plurality memory sectors, and verifies that the memory cells in a selected memory sector of the plurality of memory sectors is erased. When it determines that the selected memory sector is not erased, it again erases the plurality of memory sectors and again verifies whether the selected memory sector is erased. The erasing of the plurality of memory sectors is repeated until it is verified that the memory cells in the selected memory sector is erased.

Fast-erase memory devices and method for reducing erasing time in a memory device

A voltage boost circuit ( ) for a flash memory ( ) includes a boosting circuit ( ), which is capable of boosting a portion of a power supply voltage (V ) of the flash memory to a word line voltage level adequate for accessing a core cell in a core cell array ( ) of the memory. The voltage boost circuit further includes a balancing or clamping circuit ( ) for providing a nonzero adjustment voltage (V ) to the boosting circuit to reduce the portion of the supply voltage that is available for boosting by the boosting circuit when the power supply voltage exceeds a certain value.

Voltage boost level clamping circuit for a flash memory

A flash memory having word line decoding and selection architecture is described. The flash memory include first and second sectors of memory cells, first and second local driver circuits, first, second and third decoding circuits, and a driving circuit. The first sectors of first memory cells include a first plurality of word lines coupled to the first memory cells, each being capable of being a first selected word line. The second sectors of second memory cells include a similar Local driver circuits are independently coupled to each word line of the first and second pluralities of word lines of the first sectors. Each decoding circuits comprise a first and a second side of decoding circuitry. The first side of decoding circuitry activates a first selected plurality of local driver circuits and the second side of decoding circuitry activates a second selected plurality of local driver circuits. The second decoding circuits are coupled to the first local driver circuits and supply a first boosted voltage to the first selected word line coupled to a first local driver circuit. The third decoding circuits are coupled to the second local driver circuits and supply a second boosted voltage to the second selected word line. The driving circuit supplies a series of boosted voltages to the first decoding circuits, the second decoding circuits, the third decoding circuits, the first local driver circuits, and the second local driver circuits.

Word line decoding architecture in a flash memory

A flash memory device (,) includes a core cell array including two banks (,) of core cells and address decoding circuitry (,) and a write protect circuit. The write protect circuit includes sector write protect circuits (,) associated with respective sectors (,) of the core cell array in storing write protect data for the associated sector. The write protect circuit further includes a switch circuit (,) which selects one sector write protect signal in response to a write select signal to produce a combined write protect signal. The write protect circuit further includes an output circuit (,) coupled to the switch circuit to produce a sector write protect signal.

High speed sensing to detect write protect state in a flash memory device

A voltage boost circuit (,) for a memory (,) includes a boosting circuit (,) which is coupled to a boosted node (,) to boost a word line voltage for accessing a core cell of the memory. The voltage boost circuit further includes a reset circuit (,) coupled to the boosted node and including a switchable zero-threshold transistor (,) for resetting the boosted node to a reset voltage (VCC).

Voltage boost reset circuit for a flash memory

An address buffering and decoding architecture for a multiple bank (or N bank) simultaneous operation flash memory is described. For the duration of a read operation at one bank of the N banks, a write operation can only be performed on any one of the other N-1 banks. For the duration of a write operation at one bank of the N banks, a read operation can only be performed on any one of the other N-1 banks. The address buffering and decoding architecture includes a control logic circuit, an address selection circuit located at each of the N banks, and address buffer circuitry. The control logic circuit is used to generate N read select signals to select one bank of the N banks for a read operation and N write select signals to select another bank of the N banks for a write operation. Each address selection circuit is configured to receive from the control logic circuit a respective one of the N read select signals and a respective one of the N write select signals. The address buffer circuitry is used to simultaneously provide a write address and a read address in order to access core memory cells. Respective first portions of the write and read addresses are provided to the control logic circuit to generate the respective N read select signals and N write select signals. Respective second portions of the write and read addresses are provided to the respective address selection circuit.

Multiple bank simultaneous operation for a flash memory

A burst read mode operation is provided that boosts the voltage of a word line while the bit lines of the row are selected for reading. When the column group address bits read the last column group of cells in the row, a pulse signal is generated which temporarily reduces the boosted voltage to allow the X-decoder to select the next word line. An alternative delay element is also provided which generates an ATD pulse with a longer duration when the column group address bits are at the end of a row and a shorter duration pulse at other times.

Growing community of inventors

San Jose, CA, United States of America

Kendra Nguyen