Cypress Semiconductor Corporation

Kendall V Castor-Perry

Harold Kutz

Eashwar Thiagarajan

Hans Klein

Dennis Raymond Seguine

Mark E Hastings

Jaskarn Singh Johal

Jean-Paul Vanitegem

Anasuya Pai Maroor

Erhan Hancioglu

Bruce E Byrkett

Ata Khan

Carl Liepold

Onur Ozbek

Amsby D Richardson, Jr

Monte F Mar

Gajender Rohilla

Bert Sullam

Hans Van Antwerpen

Rajiv Singh

Andrew C Page

Implementations disclosed describe a programmable analog subsystem (PASS) having a plurality of reconfigurable analog circuits. The PASS may be coupled to an input/output device to receive an input signal and to an interface to communicate data with a central processing unit. In a first PASS configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the PASS may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the first output value, the PASS may reconfigure the plurality of reconfigurable analog circuits into a second PASS configuration having a second configuration setting, such that the second configuration setting is different than the first configuration setting.

Ultra-low power adaptively reconfigurable system

An integrated circuit device can include at least one input; at least one output configured to provide a multi-bit output value; at least one input; at least one output configured to provide a multi-bit output value; a plurality of configurable digital filter circuits; and switch circuits coupled to the at least one input and to the at least one output, the switch circuits configurable to connect same digital filter circuits as a single processing path or separate processing paths.

Integrated circuit device with reconfigurable digital filter circuits

A first analog block includes a first plurality of switched capacitors and a second analog block includes a second plurality of switched capacitors. A switch associated with the first plurality of switched capacitors as well as a switch associated with the second plurality of switched capacitors may be configured based on one or more analog functions. The configuring of the first analog and the second analog block may include the configuring of the switch associated with the first plurality of switched capacitors when the analog function is associated with a first single ended signal and the configuring of both the switch associated with the first plurality of switched capacitors and the switch associated with the second plurality of switched capacitors when the analog function is associated with a differential signal.

Programmable switched capacitor block

An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, a plurality of reconfigurable analog circuit blocks, at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; and a digital section comprising digital circuits; wherein each analog block includes dedicated of signal lines coupled to the at least one analog routing block.

Integrated circuit device with programmable analog subsystem

A first portion of a programmable switched capacitor block includes a first plurality of switched capacitors and a second portion of the programmable switched capacitor block includes a second plurality of switched capacitors. A first switch associated with the first plurality of switched capacitors as well as a second switch associated with the second plurality of switched capacitors may be configured based on a type of analog function that is to be provided. The configuring of the first analog and the second analog block may include the configuring of the first switch associated with the first plurality of switched capacitors when the analog function operates on a first single ended signal and the configuring of both the first and second switches when the analog function operates on a differential signal.

An integrated circuit (IC) device can include a plurality of analog blocks, including at least one fixed function analog circuit, and at least one reconfigurable analog circuit block selected from: a continuous time (CT) block comprising a plurality of reconfigurable amplifier circuits and a discrete time block comprising amplifiers with a reconfigurable switch network; an analog multiplexer (MUX) configured to selectively connect any of a plurality of input/outputs (I/Os) of the IC device to the analog blocks, the analog MUX including at least one low noise signal path pair having a lower resistance than other signal paths of the analog MUX; at least one analog routing block reconfigurable to provide signal paths between any of the analog blocks; a digital section comprising digital circuits; and a processor interface coupled to the analog blocks.

A clock synthesis system may include a feed forward divider circuit configured to divide a source clock signal by one of a plurality of integers in response to a select signal to generate a reference clock that is synchronous to a synchronous pulse; a modulator that modulates the select signal in response to at least a difference value; a multiplier circuit that frequency multiplies the reference clock to generate an output clock; and a timing circuit that generates the difference value in response to the source clock and synchronous pulse.

Clock synthesis systems, circuits and methods

Left and right stereo channels L and R are provided to a first set of two or more speakers of a speaker array. A bass signal B is applied to a second set of one or more speakers of the speaker array. The level of L and R applied to the first set of speakers is increased as the first set of speakers is rotated to become more horizontally aligned. The level of B applied to the first set of speakers is decreased as the first set of speakers is rotated to become more horizontally aligned.

Adapting audio signals to a change in device orientation

A resistive divider circuit may be operatively coupled with a modulated resistor circuit, wherein the resistive divider circuit and the modulated resistor circuit for an effective resistor circuit providing an effective attenuation. A variable duty cycle signal modulates the modulated resistor circuit to control the effective attenuation.

Common mode trimming with variable duty cycle

Apparatuses and methods of integrating power supply unit (PSU) control and power line communication (PLC) to transmit data on a power line in a transmitting node. One method modulates a switching frequency of the PSU between multiple spread frequencies to transmit the data.

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Seattle, WA, United States of America

Kendall V Castor-Perry