Hitachi, Ltd.

Tonen Corporation

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Advanced Life Science Institute, Inc.

Terumo Corporation

Japan As Represented by President of National Cancer Center

Other

Jiro Hitomi

Ken Yamaguchi

Tatsuya Teshima

Kenichi Osada

Masatada Horiuchi

Hiroshi Mizuta

Kiyoo Itoh

Takayuki Kawahara

Toshiyuki Mine

Hideo Sunami

Toshikazu Shimada

Toshiyuki Usagawa

Kazuo Nakazato

Naoki Kitai

Yoshikazu Saito

Shinichiro Kimura

Yoshio Miyake

Tatsuji Kimura

Kazuki Sasaki

Yoshiaki Takemura

Kae Sato

Tokujiro Yamamura

Susumu Takahashi

Toshiaki Masuhara

Tadashi Fukuzawa

Tomihiro Hashizume

Kensuke Ogawa

Eiichi Maruyama

Toshio Katsuyama

Yasuhiro Shiraki

Michiharu Nakamura

Hiroshi Kakibayashi

Kenji Hiruma

Shirun Ho

Yoshimasa Murayama

Yoshifumi Katayama

Yuji Suwa

Masaaki Fujimori

Yasushi Sawada

Takashi Uchino

Hisao Nakashima

Gerard P Morgan

Koichi Nagasaki

Sumiya Eto

Keiichi Haraguchi

Masamits Yazawa

The present invention relates to a method of concentrating low molecular weight peptides in the supernatant of serum-free cultured cells, said method comprising allowing the peptides to bind to a strong cation exchanger under an acid condition, and eluting them under an alkali condition to concentrate the peptide. Furthermore, peptides having the amino acid sequence as set forth in SEQ ID NO: 1 or 2, and a method of screening cancer markers using antibody to these peptides, are disclosed.

Search for cancer markers by a novel screening method

Search for cancer markers by a screening method

A semiconductor device includes a plurality of memory cells, and an error-correction circuit. Its write operation is performed by a late-write method, and ECC processing is executed in parallel with writing to shorten a cycle time. Moreover, when a memory cell is power-supplied through a well tap, the same address is not assigned while the memory cell is power-supplied through the well tap.

Semiconductor memory device layout comprising high impurity well tap areas for supplying well voltages to N wells and P wells

A controllable conduction device in the form of a transistor comprises source and drain regionsbetween which extends a conduction path P for charge carriers, a gatefor controlling charge carrier flow along the conduction path and a multiple layer structureproviding a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Controllable conduction device with electrostatic barrier

A semiconductor device comprises, a plurality of memory cells, and an error-correction circuit, wherein write operation is performed by a late-write method, and ECC processing is executed in parallel with writing, and thereby cycle time is shortened. Moreover, it is better that when a memory cell is power supplied through a well tap, the same address is not assigned while the memory cell is power supplied through the well tap.

Semiconductor device

A method for producing a semiconductor device which comprises causing a dopant present in a semiconductor substrate to segregate in the surface of said semiconductor substrate, thereby forming a thin layer which has a higher dopant concentration than said substrate. The thin layer formed by segregation prevents punch-through which occurs as the result of miniaturization of MOSFET. This method permits economical delta doping without sacrificing the device characteristics.

Semiconductor device and its production method

A higher-performance short channel MOS transistor with enhanced resistance to soft errors caused by exposure to high-energy rays is realized. At the time of forming a deep source/drain diffusion layer region at high density, an intermediate region of a density higher than that of impurity of a semiconductor substrate is formed between the source/drain diffusion layer and the semiconductor substrate of a conduction type opposite to that of the source/drain diffusion layer. The intermediate region is formed with a diffusion window for forming the source/drain, an intermediate layer of uniform concentration and uniform width can be realized at low cost.

Semiconductor devices and their fabrication methods

In a semiconductor memory device such as a DRAM, a conductive film is arranged on the rim portion of a isolation insulating film in opposition to a semiconductor substrate with a thin insulating film in between. This conductive film is electrically connected to a lower electrode of a storage capacitor. This novel arrangement can control the location of electrical pn junction independently of the location of metallurgical pn junction, thereby realizing a semiconductor memory device having a long data retention time with the increase in leakage current suppressed.

Method of fabricating a memory device having a long data retention time with the increase in leakage current suppressed

A bovine- or human-derived calcium-binding protein with a prescribed amino acid sequence, a method for its production, and antibodies against the protein and uses thereof.

Calcium-binding proteins

A controllable conduction device in the form of a transistor comprises source and drain regions,between which extends a conduction path P for charge carriers, a gate,for controlling charge carrier flow along the conduction path and a multiple layer structure,providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

Controllable conduction device

In a semiconductor memory device such as a DRAM, a conductive film (1.11') is arranged on the rim portion of a isolation insulating film (1.2) in opposition to a semiconductor substrate (1.1) with a thin insulating film in between. This conductive film (1.11') is electrically connected to a lower electrode (1.11) of a storage capacitor. This novel arrangement can control the location of electrical pn junction independently of the location of metallurgical pn junction, thereby realizing a semiconductor memory device having a long data retention time with the increase in leakage current suppressed.

Semiconductor memory device having a long data retention time with the

Semiconductor logic element and apparatus using thereof

A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.

DNA encoding novel calcium-binding proteins

Growing community of inventors

Fuchu, Japan

Ken Yamaguchi