International Business Machines Corporation

Cisco Technology, Inc.

Lenovo (singapore) Pte. Ltd.

Cisco Systems Inc.

Ken Van Vu

Srinivasan Ramani

Brian Michael Rogers

Ganesh Balakrishnan

Anoop Ghanwani

Clark Debs Jeffries

Mohammad Peyravian

Jeffrey Haskell Derby

Gerald Arnold Marin

Anil Krishna

Robert Allen Shearer

Gordon Taylor Davis

Hans Mikael Jacobson

Miguel Comparan

Andrew D Hilton

Brad Alan Makrucki

Alfred T Watson, Iii

Willibald A Doeringer

Gordon Bernard Bell

Haldon J Sandick

Pradip Bose

Michael Stephen Floyd

Malcolm Scott Ware

Malcolm Scott Allen-Ware

Heather Lynn Hanson

Bishop Chapman Brock

John E Drake, Jr

Tejas S Karkhanis

Raif O Onvural

Douglas H Dykeman

Erika Gunadi

Liang Li

David John Palframan

Nan Ni

Steve Woolet

Claude R Galand

Norman Clark Strole

Marcia Lambert Peters

Lap Thiet Huynh

Timothy Hume Heil

Aline Fichou

Ronald Pete Luijten

Dongming Hwang

Harold D Dykeman

Men-Chow Chiang

Jeffrey Powers Bradford

Levent Gun

Metin Aydemir

Serge Fdida

Kartik Sudeep

Bouchung Lin

Muawya Mohamed Al-Otoom

Mazin Sami Yousif

A method and circuit arrangement provide support for a hybrid pipeline that dynamically switches between out-of-order and in-order modes. The hybrid pipeline may selectively execute instructions from at least one instruction stream that require the high performance capabilities provided by out-of-order processing in the out-of-order mode. The hybrid pipeline may also execute instructions that have strict power requirements in the in-order mode where the in-order mode conserves more power compared to the out-of-order mode. Each stage in the hybrid pipeline may be activated and fully functional when the hybrid pipeline is in the out-of-order mode. However, stages in the hybrid pipeline not used for the in-order mode may be deactivated and bypassed by the instructions when the hybrid pipeline dynamically switches from the out-of-order mode to the in-order mode. The deactivated stages may then be reactivated when the hybrid pipeline dynamically switches from the in-order mode to the out-of-order mode.

Processor with hybrid pipeline capable of operating in out-of-order and in-order modes

Aspects of an embodiment of the invention disclose a method, computer program product, and system for managing the energy efficiency of servers providing multi-class computing services with Quality of Service (QoS) assurance. Computing resources are clustered into at least three groups, where each group has a separate power management policy (PMP). A plurality of requests are received from a plurality of devices, and are sorted into at least three service classes based on the requests' QoS criteria. Each request is assigned to one of at least three service queues based on the request's service class, and each service group is processed by a group of computing resources. The power management policies are configured such that each group of computing resources may service requests at an energy efficient point while meeting the QoS criteria of the service class.

Managing servers with quality of service assurances

A model-based virtual power management driven multi-chip system simulator generates utilization data and performance data with a workload model that models one or more types of workloads based on parameters that characterize the one or more types of workloads. The simulator generates thermal data and power consumption data with a power model that models power consumption at a chip-level and a system-level. The simulator then generates performance counter information with a performance model that models change of performance counters over time and at least one of the generated utilization data and the generated performance data as input to the performance model. The simulator provides this generated data as input to a driver of the simulator.

Virtual power management multiprocessor system simulation

A method for managing processor power optimization is provided. The method may include receiving a plurality of tasks for processing by a processor environment. The method may also include allocating a portion of a compute resource corresponding to the processor environment to each of the received plurality of tasks, the allocating of the portion being based on both an execution time and a response time associated with each of the received plurality of tasks.

Processor power optimization with response time assurance

A mechanism is provided for optimizing energy efficiency in a set of processor cores while maintaining application performance for a set of applications. A quality of service (QoS) level is received for one or more active applications in the set of applications and state information associated with each processor core in the set of processor cores is identified. Responsive to the QoS level and the state information indicating an action to be implemented, a change is implemented to reduce power utilization by one or more processor cores in the set of processor cores in the data processing system, where the change is via at least one of dynamic frequency scaling, dynamic voltage scaling, or core folding.

Energy efficient optimization in multicore processors under quality of service (QoS)/performance constraints

An apparatus for lock acquisition is disclosed. A method and a computer program product also perform the functions of the apparatus. The apparatus includes a lock history module that adds a current contention state of a lock to a contention history. The lock includes a memory location for storing information used for excluding access to a resource by one or more threads while another thread accesses the resource. The apparatus, in some embodiments, includes a combination module that combines the contention history with a lock address for the lock to form a predictor table index, and a prediction module that uses the predictor table index to determine a lock prediction for the lock. The prediction includes a determination of an amount of contention.

Global lock contention predictor

A method for lock acquisition includes adding a current contention state of a lock to a contention history. The lock includes a memory location for storing information used for excluding accessing a resource by one or more threads while another thread accesses the resource. The method includes combining the contention history with a lock address for the lock to form a predictor table index, and using the predictor table index to determine a lock prediction for the lock. The prediction includes a determination of an amount of contention.

A method, system and computer-usable medium are disclosed for a lock-spin-wait operation for managing multi-threaded applications in a multi-core computing environment. A target processor core, referred to as a 'spin-wait core' (SWC), is assigned (or reserved) for primarily running spin-waiting threads. Threads operating in the multi-core computing environment that are identified as spin-waiting are then moved to a run queue associated with the SWC to acquire a lock. The spin-waiting threads are then allocated a lock response time that is less than the default lock response time of the operating system (OS) associated with the SWC. If a spin-waiting fails to acquire a lock within the allocated lock response time, the SWC is relinquished, ceding its availability for other spin-waiting threads in the run queue to acquire a lock. Once a spin-waiting thread acquires a lock, it is migrated to its original, or an available, processor core.

Lock spin wait operation for multi-threaded applications in a multi-core computing environment

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Cary, NC, United States of America

Ken Van Vu