Kabushiki Kaisha Toshiba

Toshiba Chemical Corporation

Kyocera Corporation

Ken Uchida

Shinetsu Fujieda

Junji Koga

Akira Yoshizumi

Masumi Saitoh

Ryuji Ohba

Yoshihiko Nakano

Hiroshi Shimozawa

Naoko Kihara

Shuzi Hayase

Michiya Higashi

Nobukazu Suzuki

Shinji Murai

Masao Yamamoto

Shuji Yamada

Motoya Kanda

Shuji Hayase

Hirokazu Niki

Akira Toriumi

Akinori Hongu

Shinji Tsuruta

Yuu Kondou

Kunihiko Sasaki

Yoshiko Kanazawa

Kazuhiro Sawai

Tsutomu Nagata

Shinji Murakami

Shigeyuki Kouchiyama

Koji Hashimoto

Hiroshi Watanabe

Shinobu Fujita

Yasuyuki Hotta

Kazuya Matsuzawa

Yukio Nakabayashi

Hitoshi Itoh

Yoshitake Terashi

Satoru Abe

Kazutaka Matsumoto

Masanobu Watanabe

Chikako Iwaki

Hisaki Sato

Akiko Ohata

Tetsuzo Yamamoto

Ken Okuda

Tatsumi Ikeda

Kiichi Ito

Shinichi Kazama

Akira Yoshizumo

Koji Hasimoto

Kiyoaki Suzuki

Takahiro Nakauchi

A resin composition for semiconductor encapsulation, containing (A) an epoxy resin, (B) a phenolic resin-based curing agent, (C) an inorganic filler, and (D) amorphous carbon, wherein the amorphous carbon of the component (D) contains 30 atomic % or more of an SPstructure and 55 atomic % or less of an SPstructure.

Resin composition for semiconductor encapsulation and semiconductor device

The pressurized water reactor according an embodiment comprises: a cylindrical reactor pressure vessel () to which inlet nozzles are connected; fuel assemblies which are contained within the reactor pressure vessel (); a cylindrical reactor core barrel () which surrounds the fuel assemblies and forms an annular downcomer () between the reactor core barrel () and the inner surface of the reactor pressure vessel (); and radial supports. The radial supports are supports which are arranged below the downcomer () at intervals in the circumferential direction, each has vertical flow path formed therein, and position the reactor core barrel () and the reactor pressure vessel (). The radial supports each has, for example, a flow path-equipped radial keys () and a key groove member ().

Pressurized water reactor

A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a (100) plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.

Semiconductor device and manufacturing method of same

A FinFET and nanowire transistor with strain direction optimized in accordance with the sideface orientation and carrier polarity and an SMT-introduced manufacturing method for achieving the same are provided. A semiconductor device includes a pMISFET having a semiconductor substrate, a rectangular solid-shaped semiconductor layer formed at upper part of the substrate to have a top surface parallel to a principal plane of the substrate and a sideface with a () plane perpendicular to the substrate's principal plane, a channel region formed in the rectangular semiconductor layer, a gate insulating film formed at least on the sideface of the rectangular layer, a gate electrode on the gate insulator film, and source/drain regions formed in the rectangular semiconductor layer to interpose the channel region therebetween. The channel region is applied a compressive strain in the perpendicular direction to the substrate principal plane. A manufacturing method of the device is also disclosed.

A non-volatile semiconductor storage device includes: a semiconductor substrate; a source region and a drain region formed in the semiconductor substrate so as to be separated from each other; a first insulating film formed between the source region and the drain region, on the semiconductor substrate; a floating electrode formed on the first insulating film and including a semiconductor conductive material layer having extension strain; a second insulating film formed on the floating electrode; and a control electrode formed on the second insulating film. The extension strain of the floating electrode becomes gradually small as the location advances from the second insulating film toward the first insulating film, and the floating electrode has extension strain of 0.01% or more at an interface between the floating electrode and the second insulating film, and has extension strain less than 0.01% at an interface between the floating electrode and the first insulating film.

Non-volatile semiconductor storage device and method for manufacturing the same

A multi-gate field effect transistor includes: a plurality of semiconductor layers arranged in parallel on a substrate; source and drain regions formed in each of the semiconductor layers; channel regions each provided between the source region and the drain region in each of the semiconductor layers; protection films each provided on an upper face of each of the channel regions; gate insulating films each provided on both side faces of each of the channel regions; a plurality of gate electrodes provided on both side faces of each of the channel regions so as to interpose the gate insulating film, provided above the upper face of each of the channel region so as to interpose the protection film, and containing a metal element; a connecting portion connecting upper faces of the gate electrodes; and a gate wire connected to the connecting portion.

Multi-gate field effect transistor and method for manufacturing the same

A semiconductor device capable of realizing low-voltage drivability and large storage capacity (miniaturization) by achieving large threshold voltage shifts and long retention time while at the same time suppressing variations in characteristics among memory cells is disclosed. The device includes a semiconductor memory cell having a channel region formed in a semiconductor substrate, a tunnel insulator film on the channel region, a charge storage insulator film on the tunnel insulator film, a control dielectric film on the charge storage film, a control electrode on the control dielectric film, and source/drain regions at opposite ends of the channel region. The memory cell's channel region has a cross-section at right angles to a direction along the channel length, the width W and height H of which are each less than or equal to 10 nm.

Semiconductor device

A logic apparatus comprises a first single-electron device formed of a first conductive island, two first tunnel barriers with the first conductive island interposed, first and second electrodes, and a first charge storage region, and a second single-electron device formed of a second conductive island, second tunnel barriers with the second island interposed, third and fourth electrodes, and a second charge storage region, the first electrode of the first single-electron device being connected to the third electrode of the second single-electron device being connected to each other.

Logic apparatus and logic circuit

A random number generating circuit can generate random numbers with high randomness, and can be made as a compact integrated circuit. The random number generating circuit includes an uncertain logic circuit having a flip-flop type logic circuit that gives digital output values not determined definitely by a digital input value, and an equalizing circuit having an exclusive OR operating circuit for equalizing appearance frequencies of '0' and '1' in the digital output values output from the uncertain logic circuit.

Random number generating circuit

A static random access memory has first and second complementary field-effect transistors. The first complementary field-effect transistor includes a semiconductor substrate, a first field-effect transistor of electron conduction type which has a first drain region constituting a Schottky junction and a gate electrode, and a first field-effect transistor of positive hole conduction type which shares the first drain region and has a shared gate electrode. The second complementary field-effect transistor includes a second field-effect transistor of electron conduction type which has a second drain region and a gate electrode, a second field-effect transistor of positive hole conduction type which shares the second drain region and has a shared gate electrode. The gate electrode shared by the first and second complementary field-effect transistors is connected to the common drain region of the mutually opposing complementary field-effect transistors, and the static random access memory has superior resistance to software errors.

Static random access memory

A logic apparatus having first and second single-electron devices connected serially or in parallel. Each of the single-electron devices includes a conductive island insulatively disposed between two tunnel barriers, which separate the conductive island from respective source/drain electrodes. A first charge storage region is insulatively disposed over and under the conductive island and a gate electrode, respectively. When charges are accumulated in the charge storage region, a Coulomb oscillation of the respective device is shifted by a half-period from the Coulomb oscillation that results when no charge has accumulated therein.

A gate oxide film formed on the surface of a silicon substrate is partly reduced in thickness or &ldquo;thinned&rdquo; at its specified part overlying a source region. In a gate region, a multilayer structure is formed which includes a first polycrystalline silicon or &ldquo;polysilicon&rdquo; film of a p-type conductivity, a tunnel oxide film, and a second p-type polysilicon film in this order of lamination. The source region and the first polysilicon film make up a high-concentration impurity-doped pn junction with a thin silicon oxide film laid therebetween, providing a tunnel diode also known as Esaki diode. The diode is used for a negative differential resistance. Further, a portion between the first and second polysilicon films is a non-linear tunnel resistor, which serves as a load. The negative differential resistance and the load are serially connected together between a low-voltage power supply (ground potential) Vss and a high-voltage power supply Vdd, thus enabling forming a transistor with a built-in bistable circuit. Potential information of the first polysilicon film for use as a data storage node is read with a transistor amplification applied thereto. Thus, data read is performed at high speeds. Simultaneously, a current flowing between the power supplies is suppressed to a lower level, thereby minimizing power consumption in wait modes.

Semiconductor device with negative differential resistance characteristics

A nonvolatile semiconductor storage element which has a charge stored layer as a floating gate, and whose storage time is made sufficiently long. The storage element comprises a channel region formed between a source region and a drain region; first and second tunnel insulator layers formed over the channel region and through which electrons can directly tunnel quantum-mechanically; and a conductive particle layer which is sandwiched in between the first and second tunnel insulator layers; the charge stored layer being formed on the second tunnel insulator layer. An energy level at which the information electron in the charge stored layer is injected is lower than the energy level of a conduction band edge in the channel region.

Semiconductor storage element

Semiconductor device, and method of fabricating the same

Growing community of inventors

Tokyo, Japan

Ken Uchida