Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Other

Ken Tatezawa

Kunio Uchiyama

Masayuki Miyazaki

Masaru Kokubo

Osamu Nishii

Hirokazu Aoki

Kiyoshi Hasegawa

Kiwamu Takada

Junichi Nishimoto

Tatsuya Kamei

A semiconductor integrated circuit which is provided with a shift scan path incorporated in each function module and a testing I/O terminal connected to a shift scan path and provided separately from a normal-operation-use I/O terminal, and which comprises, all formed on one semiconductor chip, a bus interface circuit for connecting normal-operation-use I/O terminals of a plurality of function modules to a bus, an external interface switching circuit which switches between the bus-side I/O terminal of the bus interface circuit and the testing I/O terminal of each function module for connection to an external terminal and an interface control circuit for switch-controlling the external interface switching circuit.

IC with internal interface switch for testability

A semiconductor integrated circuit device employing two clock signal generating circuits which output clock signals for distribution to an internal circuit of the device, the first and second clock signal generating circuits having different clock-settling times and the selection thereof is effected from outside of the device. A first one of the clock signal generating circuits uses, for example, a phase-locked loop circuit which has a large clock-settling time, and the second clock signal generating circuit is implemented, for example, using a delay-locked loop circuit whose clock-settling time is small, for example, 2-3 periods. Due to the selective actuation of the second clock signal generating circuit, which has a small clock-settling time, the generating of clock signals for the internal circuits can also be halted when the internal circuits of the device are halted thereby to further lower power consumption without compromising clock oscillator responsiveness.

Semiconductor integrated circuit device

A signal from a crystal resonator or an external clock signal are input from terminals xta or exta and the signal from the crystal resonator or external clock signal are selected by mode terminal mod and input to an oscillator OSC. An input clock signal ckl is frequency-divided to desired values by a divider DIV A divided clock signal clk is input as the reference clock of a phase-locked loop PLL or delay-locked loop DLL and a clock signal output by a circuit selected by a selector SEL passes via a divider DIV to be distributed to an LSI. The phase-locked loop PLL has a clock settling time of at least 40 clock periods, whereas the clock settling time of the delay-locked loop DLL is 2-3 periods.

Growing community of inventors

Kodaira, Japan

Ken Tatezawa