Kabushiki Kaisha Toshiba

The University of Tokyo

Chuo University

National Institute of Advanced Industrial Science and Technology

Kabushiki Kaishi Toshiba

Rsun Corporation

Ken Takeuchi

Tomoharu Tanaka

Kenichi Imamiya

Takashi Mori

Seiichi Aritome

Hiroshi Nakamura

Kazuhiro Shimizu

Hideko Oodaira

Tamio Ikehashi

Koji Hosono

Fumitaka Arai

Riichiro Shirota

Kazuhito Narita

Susumu Fujimura

Toru Tanzawa

Yuji Takeuchi

Hiroshi Watanabe

Toshitake Yaegashi

Noboru Shibata

Kazushige Kanda

Takuya Futatsuyama

Kazunori Ohuchi

Toshihiko Himeno

Koji Sakui

Yoshihisa Iwata

Koichi Kawai

Makoto Takamiya

Koichi Ishida

Takayasu Sakurai

Yoshihisa Sugiura

Tadashi Yasufuku

Mayumi Fukuda

Hitoshi Shiga

Yasushi Kameda

Shuhei Tanakamaru

Teruyoshi Hatanaka

Kosuke Miyaji

Hiroshi Maejima

Yasuo Itoh

Katsuaki Isobe

Hiroki Fujii

Shigeki Sakai

Takumi Abe

Mitsue Takahashi

Kazuhide Higuchi

Takahiro Yodo

Kousuke Miyaji

Shouyu Wang

Koh Johguchi

Tomoko Iwasaki

Chao Sun

When a data utilization ratio R which is a utilization ratio of sectors in one page is not lower than a threshold value Rthand when write data is not frequently-rewritten data, a flash memory is controlled such that the write data is stored into the flash memory. When the data utilization ratio R which is the utilization ratio of sectors in one page is lower than the threshold value Rthor when the write data is frequently-rewritten data although the data utilization ratio R is not lower than the threshold value Rth, a ReRAM is controlled such that the write data is stored into the ReRAM. This suppresses deterioration of the flash memory.

Memory controller, data storage device and memory control method using data utilization ratio

To improve a reading speed and a writing speed while preventing occurrence of disturbance in a resistance storage element, specifically, a nonvolatile storage device that has a memory having at least one nonvolatile resistance storage element and a control unit configured to write a high resistance state or a low resistance state to the resistance storage element, wherein the control unit applies a bias to the resistance storage element in a verification operation carried out after writing the high resistance state, or applies a bias to the resistance storage element in a verification operation carried out after writing the low resistance state, these biases being in directions opposite to each other.

Nonvolatile storage device and method of controlling the same

To reduce deterioration of non-volatile memory and write data at higher speed, writing data is stored in a ReRAM when a page utilization rate R is lower than a threshold Rthand/or the writing data is frequently-rewritten data. With an empty space Sempin the ReRAM being less than a threshold Sth (step S), when the data in the ReRAM is infrequently-rewritten data and the page utilization rate R obtained if target data is stored in a flash memoryis equal to or higher than a threshold value Rth(steps Sand S), data of logical sectors contained in N logical page addresses stored in a transfer list is read from the ReRAM to be written to the flash memory (steps Sto S). These steps reduce deterioration of the flash memory and allow higher data writing.

Memory controller, data storage device, and memory control method

A semiconductor storage device includes at least one memory from among a primary memory, a mirror memory storing data corresponding to data stored in the primary memory, and a buffer memory; and a controller that controls the at least one memory so as to store data in the at least one memory and read data from the at least one memory.

Semiconductor storage device and control method for same

One package contains a plurality of memory chips. Each memory chip has an I/O terminal which generates a busy signal. The busy signal enables a busy state when a power supply voltage value reaches a specified and guaranteed range after a power-on sequence. The busy signal maintains the busy state until completion of initialization operations for the plurality of memory chips. The busy signal releases the busy state after completion of all initialization operations for the plurality of memory chips.

Semiconductor memory device having a plurality of chips and capability of outputting a busy signal

A booster circuit is configured, such that: in response to a reading request for reading data from a flash memory, when a voltage of an output terminal detected by a voltage detection circuit is not higher than a voltage, an oscillator outputs a control clock signal of predetermined on time and off time to a transistor of a boost converter to perform switching control of the transistor; and when the voltage detection circuit detects that the voltage of the output terminal reaches a voltage, an oscillator outputs a control clock signal of an on time and an off time input from a selection circuit to a transistor of a boost converter to perform switching control of the transistor.

Integrated circuit device

The SSD performs to encode input data from the host device into BCH code having data length and code length sequentially and controls RRAM to stores the encoded data when the write requesting signal is input from the host device. When the number of BCH code that becomes data of one page of the flash memory after being decoded is stored to RRAM, the SSD controls RRAM to read out data stored in RRAM, performs error correction and decoding to the read data as BCH code having the data length and the code length, and controls the flash memory to store the encoded data.

Control device and data storage device having a plurality of memories and error correction where a data length and a code length are set to tend to be longer as a number of writes and erases increases

The interposeris disposed on an upper surface of the stacked structureformed by stacking a plurality of a DRAM chipand a plurality of a flash memory chip. Thus down-size of an entire device is accomplished. A boost converter having an inductor is used as a voltage boost circuit. Thus down-size of the entire device is accomplished.

Stacked structure with a voltage boosting supply circuit

When detected number of errors data Nerror exceeds the upper limit number of errors Nmax, an error correction circuit of a memory controller stores twice as long data length as stored data length for execution Sdata as the data length for execution Sdata in a correction information memory unit, and code length Scref longer than the data length for execution Sdata and detectable more errors than the upper limit number of errors as the code length for execution Scode in the correction information memory unit(step Sand S). The error correction circuit encodes input data using BCH code having the stored code length for execution Scode, stored encoded data in a semiconductor memory device, is input data stored in the semiconductor memory device, performs error correction for input data using BCH code, and decode error corrected data.

Data input / output control device and semiconductor memory device system

A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

Semiconductor memory device capable of realizing a chip with high operation reliability and high yield

When write data D is high rewritten data, a PCcontrols a DRAMto store the write data D (steps Sand S). When the write data D is not the high rewritten data, the PCoutputs an RRAM write request signal and the write data D to an SSD (step Sand S). A memory controller of the SSD input the RRAM write request signal controls the RRAM and an SRAM to store the write data D in the RRAM or the SRAM. This treatment enables data stored in the DRAM to be rewritten frequently. Therefore, the decrease of number of times of refresh operation of the DRAM and the decrease of power consumption are accomplished.

Data processing apparatus, control device and data storage device

When write request signal is input from a host device, an SSD inputs data input from the host device in an encoder sequentially and controls a RRAM to store data output from the encoder. When size of data stored in the RRAM reaches predetermined size Sref, the SSD controls the RRAM to read out data of size of the predetermined size Sref, inputs read data from the RRAM in the encoder, and controls a flash memory to store data output from the encoder. This configuration accomplishes the increase of the data write speed and improvement of reliability of the data.

Data storage device and control device configured to control data transfer between a host device, a first storage, and a second storage

The channel number detecting circuit detects the operation channel number based on the output terminal voltage after falling down when the output terminal voltage falls down during the voltage boosting control, and the switching control circuit generates the control clock signal having the on-time and the off-time adjusted based on the operation channel number and performs the voltage boosting control using generating control clock signal. The voltage boosting control is properly performed based on the operation channel number when the operation channel number increase during performing the voltage boosting control. Thus boosting the power supply voltage up to a second voltage is accomplished.

Integrated circuit device having a plurality of integrated circuit chips and an interposer

A non-volatile semiconductor device has a memory cell array having electrically erasable programmable non-volatile memory cells, reprogramming and retrieval circuits that temporarily store data to be programmed in the memory cell array and sense data retrieved from the memory cell array. Each reprogramming and retrieval circuit has first and second latches that are selectively connected to the memory cell array and transfer data. A controller controls the reprogramming and retrieval circuits on a data-reprogramming operation to and a data-retrieval operation from the memory cell array. Each reprogramming and retrieval circuit has a multilevel logical operation mode and a caching operation mode. In the multilevel logical operation mode, re-programming and retrieval of upper and lower bits of two-bit four-level data is performed using the first and the second latches to store the two-bit four-level data in one of the memory cells in a predetermined threshold level range.

Non-volatile semiconductor memory and simultaneous writing of data

Growing community of inventors

Tokyo, Japan

Ken Takeuchi