Sharp Kabushiki Kaisha Corporation

Ken Sumitani

Haruyasu Fukui

Hidekazu Takata

Yasumichi Mori

Yuji Tanaka

Atsushi Yamashita

Hiroyuki Nabesawa

Manabu Yumoto

Manabu Onozaki

Masanobu Okano

Tsuyoshi Ono

Masahiko Watanabe

Yuta Ikawa

Hiroshi Nishioka

Ken Nakazawa

Yasuyuki Aikawa

Takayuki Satoh

An image receiving device includes an image processing unit that rotates at least one of first and second images in a process of restoring the first and second images if an image transfer signal received by the image receiving device includes the first and second images in which a direction in which a scan line of the first image extends is different from a direction in which a scan line of the second image extends.

Image display system with image rotation processing

To provide an electronic device that can detect an abnormality in an element with a simple configuration. An electronic deviceincludes: a first element string groupformed by at least one element stringtoconnected in parallel, the element stringtobeing formed by at least one element connected in series; a second element string groupformed by the element stringtobeing at least one in number and connected in parallel; and an abnormality detecting unitthat detects an abnormality in the element stringtoandtoforming at least one of the first element string groupand the second element string group, based on whether or not a first current Ibeing the sum of current flowing through the element stringtoforming the first element string groupand a second current Ibeing the sum of current flowing through the element stringtoforming the second element string groupsatisfy a prescribed relationship.

Electronic device

A light guide plate includes a plurality of LED light sources emitting light into two opposed side surfaces of the light guide plate, such that LED light sources having a length shorter than each of the opposed side surfaces at which the plurality of LED light sources are provided.

Illumination device with edge-lit light guide with opposed light sources

A light emitting module board which is compatible with a plurality of screen sizes and is used for a backlight apparatus of a liquid crystal display panel is provided. A light emitting module includes a first connectorand a second connector, each including a plurality of cathode terminals and at least one anode terminal, at each end of the board, and can be connected to another one to each other through the connectors in multi-level. A cathode wiringfor supplying a cathode control signal includes first cathode wirings which connect the cathode terminals of the first connector and light emitting bodies to supply a control signal to the light emitting bodies in the light emitting module, and second cathode wirings which connect the cathode terminals of the first and second connectors to supply a control signal to the light emitting bodies on a downstream light emitting module.

Light emitting module, light emitting module unit, and backlight system

An LED module comprises: an insulating substrate in plate form; first main and sub terminals for connection to an external circuit formed near the first side of the insulating substrate; second main and sub terminals for connection to an external circuit formed near the second side opposite to the first side; three or more connecting wires formed on the insulating substrate for connecting LEDs continuously aligned at a distance from each other in series; LEDs individually connected between the connecting wires adjacent to each other and connected in series in a same direction; and a first passing wire formed on the insulating substrate for electrically connecting the first sub-terminal to the second sub-terminal, wherein a first connecting wire located on one side is electrically connected to the first main terminal, and a second connecting wire located on the other side is electrically connected to the second main terminal.

LED module and LED light source apparatus

A semiconductor memory device arranged for minimizing the duration of time required for conducting a batch verify action and thus speeding up a buffer write action is provided. The device which conducts a write action to memory cells in an address area, a batch verify action for collectively conducting verify action for a plurality of addresses, and repeats the batch verify action and the write action, comprises a detecting means for detecting whether or not each address contains an unwritten memory cell, and conducts a verify action at least at a part of the batch verify action excluding at least a part of addresses judged not to contain unwritten memory cells by the verify action at one or more cycles before.

Semiconductor memory device

A semiconductor memory device, comprising a memory array including a plurality of memory cells capable of storing data of at least 1 bit, includes a data write control section for controlling a data write operation to the plurality of memory cells; an address signal generation section for generating an address signal which represents an address of a prescribed memory cell; a determination section for determining whether or not to write data to the prescribed memory cell and outputting a first write signal; a data register section for storing data represented by the first write signal and outputting a second write signal; and a data write section for writing data to the prescribed memory cell based on the second write signal. The data register section stores the data based on a control signal which is output by the data write control section.

Semiconductor memory device and method for writing data

A semiconductor memory device is provided, which comprises a memory array comprising a plurality of memory cells, a page buffer section for temporarily storing data to be written into the memory array, and a masking section for masking at least a portion of data read from the page buffer section.

A semiconductor memory device comprises first and second memory sections including a plurality of memory elements, and a memory control section for allowing a data transfer operation between the first and second memory sections based on an external control command while allowing a memory operation to at least one of the first and second memory sections. At least one of the first and second memory sections include a plurality of small memory regions, and the memory control section allows each of the plurality of small memory regions to be separately and simultaneously subjected to an access operation.

Semiconductor memory device, information apparatus, and method for determining access period for semiconductor memory device

A non-volatile semiconductor memory device, comprises a plurality of memory banks each including a plurality of memory cells, a command recognition section for identifying an externally input command signal and outputting an identification signal, an internal control section for generating a control signal for executing a command designated by the identification signal, an address control section for generating an internal address signal to a memory region including an arbitrary combination of the plurality of memory banks to be accessed, based on the externally input address signal, and a first address inversion section for inverting or non-inverting the logical values of at least a specific bit of the input address signal and outputting the resultant input address signal to the address control section. Predetermined memory cells are accessed based on the control signal and the internal address signal.

Non-volatile semiconductor memory device and information apparatus

A semiconductor storage device including: a memory having a memory space, a plurality of addresses of the memory space each having data stored therein; and a security circuit for controlling a security function which activates or deactivates at least a part of the memory space according to whether, in the case where an address input to the security-circuit matches at least one key-address included in the security circuit, data stored in the address in the memory space is manipulated under a condition equal to a predetermined condition or under a condition not equal to the predetermined condition.

Semiconductor storage device, control device, and electronic apparatus

A nonvolatile semiconductor storage device includes a row decoder which independently controls a plurality of row select line groups. A negative voltage generated by a debooster circuit is applied to individual row select line groups with time shifts. As a result, peaks of erase current can be suppressed, so that consumption current can be reduced. In this device, a current limiting circuit of the booster circuit limits the consumption current of the booster circuit, allowing voltages to be generated within a range under a specified current value according to the conditions of voltage application to the individual row select line groups. Thus, a further reduction of the consumption current at a shorter scale can be achieved.

Nonvolatile semiconductor storage device with limited consumption current during erasure and erase method therefor

A data transfer control device of the present invention includes: a command recognition section for recognizing the input control command; a first address output section for controlling an output and storage order of the data transfer addresses and the data transfer completion address based on the input control command; a first memory address storage section for storing the data transfer start address of the first memory array output from the first address output section; a second memory address storage section for storing the data transfer start address of the second memory array output from the first address output section; a third memory address storage section for storing the data transfer completion address output from the first address output section.

Data transfer control device, semiconductor memory device and electronic information apparatus

A semiconductor memory device in which an input command controls an operation includes a command state machine for decoding the input command and outputting the decoding result; a plurality of status registers for storing state information of the semiconductor memory device; a first switching circuit for receiving data from the plurality of status registers, and selectively outputting the data from at least one of the plurality of status registers to a first data bus; and a second switching circuit for receiving the data on the first data bus and data from a sense amplifier, and selectively outputting either one of data to a second data bus. At least the first switching circuit, among the first and second switching circuits, is controlled by the decoding result output by the command state machine.

Semiconductor memory device and information device

A semiconductor storage device includes: a plurality of first memory arrays each including a plurality of semiconductor storage elements, in which data from an external device is written, and from which the data is read out to the external device, a second memory array which operates separately from the plurality of first memory arrays and which includes at least one block including a plurality of non-volatile semiconductor storage elements; and a data transfer section for transferring the data between the plurality of first memory arrays and the second memory array.

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Tenri, Japan

Ken Sumitani