Taiwan Semiconductor Manufacturing Comp. Ltd.

Ken-Shen Chou

Shun-Liang Hsu

Hsiu-Mei Yu

Jowei Dun

Ying-Lang Wang

Yu-Ku Lin

Hui-Ling Wang

Jiun-Chung Lee

Hsiu-Chieh Cheng

In one embodiment, the disclosure relates to a method and apparatus for surface recovery of a polymer insulation layer through implantation. The method includes providing a substrate having thereon a conductive pad and an insulation layer, optionally processing the conductive pad to remove oxide layer formed on the conductive pad and conducting ion implantation to recover dielectric properties of the insulation layer.

Method and apparatus for polymer dielectric surface recovery by ion implantation

A new method is provided for the creation of a solder mask for solder bump formation. A passivation layer is deposited on the semiconductor surface in the surface of which a contact pad has been provided, an opening is created in the layer of passivation that partially exposed the surface of the contact pad. A layer of UBM metal is deposited and patterned, limiting the layer of UBM to overlying and contacting the contact pad of the solder bump. A layer of elastomer is blanket deposited over the surface and patterned, creating an opening overlying the opening created in the layer of passivation, exposing the layer of UBM. The exposed surface of the layer of UBM is electroplated with a layer of solder, using the opening created in the layer of elastomer as the self-aligned electroplating opening. A step of reflow of the electroplated solder and the layer of elastomer completes the process of the invention, creating a solder bump surrounded by a layer of cured elastomer. Solder flow and elastomer curing are performed in the same step, and a special UBM design is used for the exposure of the UBM pad.

Elastomer plating mask sealed wafer level package method

An improved method for removing residual slurry particles and metallic residues from the surface of a semiconductor substrate after chemical-mechanical polishing has been developed. The cleaning method involves sequential spray cleaning solutions of NH.sub.4 OH and H.sub.2 O, NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O, HF and H.sub.2 O, and HCl, H.sub.2 O.sub.2 and H.sub.2 O. The cleaning sequence is: 1. A pre-soak in a spray solution of NH.sub.4 OH and H.sub.2 O; 2. Spray cleaning in a solution of NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O; 3. Spray cleaning in a dilute solution of HF and H.sub.2 O; 4. Spray rinsing in DI-water. It is important that slurry particulates first be removed by NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O, followed by spray cleaning in a dilute solution of HF and H.sub.2 O to remove metallic residues. The spray cleaning method is superior to brush cleaning methods for both oxide-CMP and tungsten-CMP and results in superior removal of slurry particles and metallic residues introduced by the CMP processes. An optional spray cleaning step using a solution of HCl, H.sub.2 O.sub.2 and H.sub.2 O results in further reduction of metallic residue contamination following oxide-CMP. Compared to traditional brush cleaning the new spray cleaning process has a 2.times. improvement in throughput, less consumption of DI water, and low risk of cross-contamination between sequentially cleaned substrates.

Process for cleaning a semiconductor substrate after chemical-mechanical

A method is described for improving the step coverage of tungsten interconnects and plugs when deposited at low temperatures into contact/via openings having high aspect ratios. The depositions are made at pressures between 4.5 and 100 Torr in a CVD tool. The method includes a first nucleation step, and a second step for filling the contact/via openings wherein deposition conditions favor good step coverage. For forming an interconnect and a third deposition step, providing moderate step coverage and low stress, is used to build up the interconnect. The high pressures permit deposition at practical rates at low temperatures. In addition the high pressures also permit application of backside gas pressure to the wafer during deposition, thereby improving the thermal contact between the wafer and the heated substrate holder. This contributes significantly to stress reduction and improved step coverage.

Growing community of inventors

Hsinchu, Taiwan

Ken-Shen Chou