Texas Instruments Corporation

Ken Saitoh

Shoji Wada

Shunichi Sukegawa

Yukihide Suzuki

Kazuya Ito

Makoto Saeki

David R Brown

Tadashi Tachibana

Yasuhito Ichimura

A dynamic random access memory device having a number of sense amplifier banks (404a-404h) is disclosed. Each sense amplifier bank (404a-404h) has an associated memory array (402a-402h) and supply switch (406a-406h). In a given sense operation, data signals are coupled from a memory array (402a-402h) to its associated sense amplifier bank (404a-404h). Selection of the memory array (402a-402h) is determined by address signals (MS0-MS7). The supply switches (406a-406h) provide a sense amplifier supply voltage at a supply node (708) of its associated sense amplifier bank (404a-404h). At the initial portion of a sense operation, the supply switch (406a-406h) couples the high power supply voltage (VDD) to its associated supply node (708). After a predetermined time period, the supply switch couples a reduced array voltage (VDL) to its associated supply node (708). The switching operation is determined by an overdrive signal (SAOV). The timing of the SAOV signal is based upon the location of the memory array (402a-402h) which is being accessed in the sense operation.

Address controlled sense amplifier overdrive timing for semiconductor

A memory circuit includes a bond option circuit 106 having an input and an output, and row control circuitry 100 coupled to the output of the bond option circuit, the row control circuitry including address terminals, A12 and A13. The memory circuit also includes column control circuitry 102 coupled to the output of the bond option circuit, the column control circuitry 102 also including address terminals, A12 and A13. A memory cell array is coupled to the row control and column control circuitry and is arranged in a first plurality of banks of memory cells, the banks being selectable by a combination of address signals on the address terminals of the row control and column control circuitry. In response to a first signal at the input of the bond option circuit 106, the bond option circuit produces a second signal at the output of the bond option circuit that is coupled to the row control 100 and column control 102 circuitry. In response to the second signal, the row control and column control circuitry makes the banks of the array selectable in a second plurality. For example, the array may originally be arranged in four banks, but by the placing the proper signal at the input of the bond option circuit, the array is selectable as a two-bank array.

Memory configuration circuit and method

A semiconductor memory device in which erroneous operation with respect to undesired level changes of the input address signal is prevented, and appropriate operation of the main amplifier is ensured. The semiconductor memory device has a main amplifier activating pulse generator 112' which includes response sensitivity reduction circuit 10, response sensitivity selector 12, and main amplifier activating pulse generator 14. The response sensitivity reduction circuit 10 can reduce the response sensitivity or input sensitivity of the circuit 112' with respect to an input address transition detection pulse ATD. The response sensitivity selector 12 selects either a first input terminal A1 or a second input terminal A2, depending on the output state of the main amplifier activating pulse generator 14. Consequently, when there is no output of a main amplifier activating pulse MA from the main amplifier activating pulse generator 14, the response sensitivity selector 12 switches to first input terminal A1 to select response sensitivity reduction circuit 10; when a main amplifier activating pulse MA is output, the selector 12 switches to second input terminal A2 to select bypass circuit 11.

Semiconductor memory device

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Akishima, Japan

Ken Saitoh