Renesas Technology Corp.

Renesas Electronics Corporation

Micron Technology Incorporated

Nippon Steel Metal Products Co., Ltd.

Ken Saito

Yoshio Inoue

Koji Hirakimoto

Toshiyuki Sadakane

Kazuhiro Takahashi

Wataru Uchida

Ryoji Ishikawa

Satoshi Shibatani

Kenta Suto

Tatsuya Umeda

Shinichi Takayama

Takeshi Yuki

Kaoru Furunishi

Tsuneo Ochi

Embodiments of the disclosure are drawn to apparatuses and methods for charging memory data lines when a high charge level is to be written to a memory. The apparatus may include a write amplifier that includes one or more additional pull-up drivers for charging the memory data lines. Control logic may control when additional pull-up drivers are activated. Control logic may control when main data lines are coupled to shared data lines. Methods for charging memory data lines may include providing control signals that indicate which main data lines are coupled to shared data lines and when a write command is received. Methods may include providing a signal that is indicative of the data to be written. The control signals and signal indicative of the data to be written may be used to activate one or more pull-up drivers to charge one or more data lines.

Apparatuses for decreasing write pull-up time and methods of use

A power domain is automatically generated. A computer performs a function simulation processfor evaluating whether or not a designed circuit satisfies a specification, and a clustering processwhich obtains a power domain by clustering logical blocks in which activation timings are within a range, based on the result of the function simulation process. Since the power domain is obtained by a process performed by the computer, the power domain can be optimized compared to a case when it is obtained by hand (manual work of the designer).

Obtaining power domain by clustering logical blocks based on activation timings

An arrangement verification apparatus that makes it possible to shorten a time it takes to complete a failure/no-failure test on the arrangement of control circuits that control block circuits is provided. The arrangement verification apparatus arranges block circuits to be controlled comprising a semiconductor device and control circuits that control the block circuits over a predetermined floor and conducts a failure/no-failure test on the arrangement of the control circuits. The arrangement verification apparatus includes: a floor plan generation unit that arranges block circuits over a floor based on circuit specifications; a grouping generation unit that hierarchically groups the block circuits arranged over the floor and control circuits described in the circuit specifications based on a predetermined requirement to generate a group tree; a control circuit arrangement unit that arranges the control circuits over the floor according to a predetermined condition and the group tree generated at the grouping generation unit; and a failure/no-failure test unit that conducts a failure/no-failure test on the arrangement of the control circuits by the control circuit arrangement unit.

Arrangement verification apparatus

The present invention relates to a routing analysis method for performing a routing analysis on an integrated circuit from a netlist which is information on a plurality of cells constituting the integrated circuit and routes connecting the cells, and the routing analysis method comprises a step (Step) of obtaining the sum of areas of a plurality of cells, the number of cells or the number of routes connecting the cells from the netlist, to be defined as a constant C, and calculating a layout area S which is an area of a square layout region, by dividing the constant C by a predetermined constant U, a step (Step) of calculating a total route length L by multiplying a half perimeter length H of the layout region having the layout area S obtained in Stepby a predetermined coefficient &#x3b1;, and a step (Step) of calculating a routing difficulty index by dividing the total route length L by the layout area S. Thus, the present invention provides a routing analysis method for an integrated circuit, which, allows calculation of routing difficulty index with high accuracy of prediction.

Routing analysis method, logic synthesis method and circuit partitioning method for integrated circuit

A floor plan evaluation method by which a floor plan can be quantitatively evaluated. The floor plan evaluation method includes first extracting a plurality of specified elements, which are specified in advance from data on a floor plan which is made automatically by, e.g., a floor planner, second obtaining an individual evaluation value on each of a plurality of individual evaluation items on the basis of the plurality of specified elements extracted in the first step, and third calculating an integrated evaluation value on the floor plan on the basis of a plurality of individual evaluation values obtained in the second step. Then, a plurality of integrated evaluation values obtained by executing the first to third operations for a plurality of floor plans are compared with one another to relatively evaluate the plurality of floor plans.

Floor plan evaluating method, floor plan correcting method, program, floor plan evaluating device, and floor plan creating device

An automatic floor-planning method includes extracting a register and a logic operation cell in a semiconductor integrated-circuit unit, extracting a first register set and a second register set that are assumed to input and receive a signal to and from the logic operation cell directly or via other logic operation cell, respectively, creating a set of the logic operation cells as a cluster cell, determining a layout of the cluster cell and the register, selecting a logic level block for which a floor plan is performed, and determining an arrangement and wiring area such that the arrangement and wiring area of the logic level block includes as many cells as possible that belong to the logic level block.

Automatic floor-planning method capable of shortening floor-plan processing time

A floorplanning apparatus includes a seed position decision section for deciding a placement position of a logic seed of each hierarchical block; a cell placement section for placing cells belonging to the hierarchical block around the placement position of each logic seed; and a placement region decision section for deciding placement and routing regions of each hierarchical block considering cell placement results produced by the cell placement section.

Floorplanning apparatus deciding floor plan using logic seeds associated with hierarchical blocks

A buffer cell and an inverter cell are embedded in advance in an internal open space of each of mega-cells and IO cells composing a semiconductor integrated circuit. Thereafter, in cases where it is expected that a cross-talk noise is generated in a signal transmitting through a particular wire of the semiconductor integrated circuit, one mega-cell or one IO cell, which is placed in a position nearest to a generation position of the cross-talk noise, is selected from the mega-cells and the IO cells, and the buffer cell or the inverter cell embedded in the selected mega-cell or the selected IO cell is inserted into the particular wire. Therefore, because the capacitance between the particular wire and each wire adjacent to the particular wire is reduced, the cross-talk noise can be reduced.

Automatic cell placement and routing apparatus and automatic cell placement and routing method used for the apparatus

A metal skid for bundling is substantially shaped like a square pipe, and a series of longitudinally disposed embosses, each extending at least vertically or diagonally, are formed on each sidewall.

Growing community of inventors

Tokyo, Japan

Ken Saito