Micron Technology Incorporated

Aptina Imaging Corporation

Ken S Hunt

Andrew M Lever

David J Warner

Sion C Quinlan

Joe A Ward

Bryan Almond

Timothy Bales

Integrated circuits with amplification circuitry are provided. The amplification circuitry may have an input terminal, an output terminal, a positive power supply terminal, and a ground terminal. The amplification circuitry may include first, second, and third stages. The first stage may provide biasing for the second stage. The second stage may provide biasing for the third stage. The second stage may provide paths for conveying an input signal from the input terminal to the third stage. The second stage may bias the amplifier to have low quiescent current and low shoot-through current. The second stage may prevent PVT variations such as supply voltage variations from affecting the quiescent current and shoot-through current of the amplifier. To increase the high-frequency response of the amplifier, capacitors may be added to the paths for conveying the input signal from the input terminal to the third stage.

Circuitry for biasing amplifiers

The present invention provides a method and apparatus for a programmable capacitor associated with an input/output pad in the semiconductor device. The apparatus includes a semiconductor die having an upper surface, a first capacitor deployed above the upper surface of the semiconductor die, a separation layer deployed above the first capacitor, and a bond pad deployed above the separation layer such that at least a portion of the bond pad lies above the first capacitor.

Programmable capacitor associated with an input/output pad

An embodiment includes encoding parallel digital data into encoded and parallel digital data in an encoder and generating parallel test data in a pseudo-random binary sequence generator circuit. The encoded and parallel digital data is coupled through a multiplexer to be serialized in a serializer in a normal mode of operation and the parallel test data is coupled through the multiplexer to be serialized in the serializer in a test mode of operation. Encoded and serial digital data are transmitted to a transmission medium in the normal mode, and serial test data are transmitted to the transmission medium in the test mode. The encoder, the serializer, the sequence generator circuit, and the multiplexer may be fabricated in a single integrated circuit chip. The parallel test data may be parallel pseudo-random binary sequence data. The parallel digital data may include data to generate colors in a visual image.

DVI link with parallel test data

A voltage clamp circuit is disclosed and claimed. The voltage clamp circuit includes a bypass device and a differential sense amplifier or comparator adapted to control operation of the bypass device. The bypass device is activated in response to the differential sense amplifier or comparator sensing a voltage above a predetermined level.

Voltage clamp circuit

A full rail-to-rail CMOS comparator is provided. The comparator includes a gain stage and a bias stage. The bias stage is responsive to the common mode input voltage level to provide a bias signal that maintains the gain stage with an optimum operating range regardless of the level of the common mode input voltage, thus maintaining the comparator output responsive to the differential input voltage. Accordingly, when operating in the optimum operating range, duty cycle distortion of the signal at the comparator output is minimized. The comparator also offers improved performance due to a lower component count and fewer comparator stages, thus decreasing power consumption and improving propagation delays.

Rail-to-rail CMOS comparator

A circuit for producing an output signal at an output thereof in response to an input signal at an input thereof is comprised, in one embodiment, of a first switch for connecting the output to a first voltage source and a second switch for connecting the output to a second voltage source. A first control switch is provided for turning off the first switch in response to the logic level of the input signal while a second control switch is provided for turning off the second switch in response to the logic level of the input signal. An integrator is responsive to the input signal for turning on one of the first and second switches depending on the logic level of the input signal. A method of operating such a circuit is also disclosed.

Circuit having a controllable slew rate

An input-output (I/O) buffer and a method of biasing an I/O buffer that avoids inadvertent conduction of a pull-up transistor included in the buffer when an input signal having a voltage greater than the supply voltage is applied to the I/O buffer in an input mode. Inadvertent conduction of the pull-up transistor is avoided during an input mode by biasing the gate and the body of the pull-up transistor with a supply voltage until the voltage of the input signal exceeds the voltage of the voltage supply, at which time the voltage of the input signal is applied to the gate and the body of the pull-up transistor instead. The I/O buffer includes a driver circuit having a pull-up transistor and an I/O node to receive an input signal. The I/O buffer also includes a pull-up transistor bias circuit to provide the voltage to the gate and the body of the pull-up transistor.

Growing community of inventors

Berkshire, United Kingdom

Ken S Hunt