Harris Corporation

Ken R King

Gerald M Cotreau

David W Riemer

Celimo P Hernandez

The analog to digital converter 300 has voltage reference circuitry 326 which includes a bandgap generator and a correction circuit 5300. The bandgap generator includes first and second NPN transistors 5211-5224, 5231-5232 of differing emitter areas and an operational amplifier 5202 with inputs sensing the collector current of the first and second NPN transistors 5211-5224, 5231-5232. First and second NPN transistors 5211-5224, 5231-5232 have their bases tied together. The output of the amplifier 5202 drives the bases of the NPN transistors 5211-5224, 5231-5232 through a resistor divider 5251-5253.

Analog-to-digital converter and reference voltage circuitry

A two-step analog-to-digital converter and BiCMOS fabrication method. The fabrication method provides pseudosubstrate isolation of digital CMOS devices from the analog devices. The converter uses NPN current switching in a flash analog-to-digital converter and in a digital-to-analog converter for low noise operation. CMOS digital error correction and BiCMOS output drivers provide high packing density plus large output load handling. Timing control aggregates switching events and puts them into intervals when noise sensitive operations are inactive. The fabrication method uses a thin epitaxial layer with limited thermal processing to provide NPN and PNP devices with large breakdown and Early voltages. Laser trimmed resistors provide small long term drift due to dopant stabilization in underlying BPSG and low hydrogen nitride passivation.

Differential voltage follower

A sample and hold circuit having low distortion at a large full power bandwidth utilizes a compensation capacitor which is connected across the input and output of an output stage of the sample and hold circuit and is driven by the output current signal, i.e. slew current I.sub.S, of the input stage. A hold capacitor is also included and arranged in parallel with the compensation capacitor to be voltage driven. The hold capacitor has a capacitance much larger than that of the compensation capacitor and a voltage equal to voltage of the compensation capacitor. A switchable voltage buffer for isolating the hold capacitor from the output of the input stage and for driving the hold capacitor, independently from the slew current, to a voltage value equaling the voltage of the compensation capacitor is also provided.

Low distortion sample and hold circuit

The front end of an operational amplifier having an improved controlled slew rate and high gain current output capabilities. The amplifier includes a slew enhancement or large signal stage connected in parallel to a normal front end or small signal stage. The small signal stage supplies a transconductance output which is approximately linearly related to the input until its slew rate limit. The slew enhancement stage is designed to provide slew current when the small signal stage reaches its slew rate limit, thereby providing an increased output current response to an increasing differential input voltage beyond the slew rate of the small signal stage. Two pair of differential amplifiers are used in both a large and small signal stage as well as an improved output stage comprising of current mirrors.

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Palm Bay, FL, United States of America

Ken R King