National Semiconductor Corporation

Texas Instruments Corporation

Ken Pham

William Paul Mazotti

Luu Thanh Nguyen

Bruce Carlton Roberts

Peter Deane

Jia Liu

John P Briant

Nikhil Vishwanath Kelkar

Stephen Gee

Anindya Poddar

Roger William Clarke

Hau Thanh Nguyen

Michael R Nelson

Janet E Townsend

Rajeev Dinkar Joshi

Jaime A Bayan

Christopher James Smith

Woochan Kim

Vivek Kishorechand Arora

Siva Prakash Gurrum

Stefan Wlodzimierz Wiktor

Yongseon Koh

Cheol Hyun Han

Daryl R Heussner

Hem P Takiar

Ashok S Prabhu

Peng Soon Lim

Manu Joseph Prakuzhy

Terh Kuen Yii

Kwang-soo Kim

Mohd Sabri Bin Mohamad Zin

Luu Thanh Nquyen

Manu A Prakuzhy

An electronic device includes a multilevel ceramic body, first, second, and third plates, and first and second semiconductor dies, with the multilevel ceramic body having opposite first and second sides, a first and second openings in the first side, a third opening in the second side, and a ceramic separator structure defining first and second interior portions between the first and second openings. The first plate is attached to the first side and covers the first opening, the second plate is attached to the first side and covers the second opening, the third plate is attached to the second side and covers the third opening, the first semiconductor die is in the first interior portion, and the second semiconductor die is in the second interior portion of the ceramic body.

Half bridge ceramic hermetic package structure

This description relates generally to semiconductor devices and processes. A method for forming a packaged semiconductor package can include attaching a front side of a metal layer to a die pad of a leadframe that includes conductive terminals, so a periphery portion of the metal layer extends beyond a periphery pad surface of the die pad, and a portion of a half-etched cavity on the front side of the metal layer is located near the periphery pad surface of the die pad. The method further includes attaching a semiconductor device to the die pad and encapsulating the semiconductor device, the front side of the metal layer, a portion of a back side of the metal layer, and a portion of the conductive terminals to form a packaged semiconductor device.

Packaged semiconductor device including heat slug

A semiconductor device that has at least one semiconductor chip attached to a leadframe made of sheet metal of unencumbered full thickness. The leadframe has leads of a first subset that alternate with leads of a second subset. The leads of the first and second subsets have elongated straight lead portions that are parallel to each other in a planar array. A cover layer of insulating material is located over portions of un-encapsulated lead surfaces. The portions of the leads of the first and second subsets that don't have the cover layer have a metallurgical configuration that creates an affinity for solder wetting.

Spot-solderable leads for semiconductor device packages

A stacked die semiconductor package includes a leadframe including a die pad and lead terminals on at least two sides of the die pad, a top die having circuitry coupled to bond pads, and bottom die having a back side that is attached by die attach material to the die pad and a top side having at least one redistribution layer (RDL) over and coupled to a top metal level including connections to input/output (IO) nodes on the top metal level. The RDL provides a metal pattern including wirebond pads that match locations of the bond pads of the top die. The bond pads on the top die are flip-chip attached to the wirebond pads of the bottom die, and the bond wires are positioned between the wirebond pads and the lead terminals.

Stacked die semiconductor package

A dual leadframe () for semiconductor systems comprising a first leadframe () having first metal zones separated by first gaps, the first zones including portions of reduced thickness and joint provisions in selected first locations, and further a second leadframe () having second metal zones separated by second gaps, the second zones including portions of reduced thickness and joint provisions () in selected second locations matching the first locations. The second leadframe is stacked on top of the first leadframe and the joint provisions of the matching second and first locations linked together. The resulting dual leadframe may further include insulating material () filling the first and second gaps and the zone portions of reduced thickness, and has insulating surfaces coplanar with the top and bottom metallic surfaces.

Semiconductor systems having dual leadframes

Semiconductor systems having premolded dual leadframes

An integrated circuit package configured to incorporate a lead frame and methods for its making are is described. The package comprising an IC with aluminum bond pads in communication with circuitry of the die with lead frame with silver bond pads. The package having gold bumps bonded between the aluminum bond pad of the die and the silver bond pad of the lead frame. The package including an encapsulant envelope and including various materials and bond pad structures and constructed in a manner formed by thermosonically or thermocompressionally bonding the gold balls to the bond pads. Also, disclosed are methods of making the package.

Lead frame interconnect scheme with high power density

Methods and systems are described for enabling the efficient fabrication of wedge-bonding of integrated circuit systems and electronic systems.

Wire bonding apparatus with a textured capillary surface enabling high-speed wedge bonding of wire bonds

Wire bonding deflector for a wire bonder

An improved leadframe panel suitable for use in packaging IC dice is described. The described leadframe panel is configured such that the amount of leadframe material that is removed during singulation of the leadframe panel is reduced.

Leadframe panel

Optoelectronic components, specifically, ceramic optical sub-assemblies are described. In one aspect, the optoelectronic component includes a ceramic base substrate having a pair of angled (or substantially perpendicular) faces. The electrical traces are formed directly on the ceramic surfaces and extend between the pair of faces. A semiconductor chip assembly is mounted on the first face of the ceramic base substrate and a photonic device is mounted on the second face. Both the semiconductor chip assembly and the photonic device are electrically connected to traces on the ceramic base substrate. The semiconductor chip assembly is generally arranged to be electrically connected to external devices. The photonic devices are generally arranged to optically communicate with one or more optical fibers. The described structure may be used with a wide variety of photonic devices. It is particularly well adapted for use with vertical cavity surface emitting lasers (or laser arrays) and detectors (or detector arrays). In some embodiments, at least the cathode of the photonic device is soldered directly to a cathode pad on the base substrate. Similarly, in some embodiments, the semiconductor chip assembly is electrically connected to the base substrate by direct soldering. Specific base substrate structures are disclosed as well.

Ceramic optical sub-assembly for optoelectronic modules

The present invention provides a low cost device that has a true die to external fiber optic connection. Specifically, the present invention relates to an optical device package joined to a semiconductor device package. In some cases, the combination is joined using wirebond studs and an adhesive material. In other cases, the combination is joined using an anisotropic conductive film. Yet, in other cases, the combination is joined using solder material. Each of these joining mechanisms provides high levels of thermal, electrical and optical performance. The joining mechanisms can apply to optical sub-assembly and chip sub-assembly interfaces in transceivers, transmitters, as well as receivers for opto-electronic packages.

Techniques for joining an opto-electronic module to a semiconductor package

This disclosure describes a clear overmolding cap for protecting the photonic devices in optoelectronic packages from damage due to handling, module assembly, board assembly, and environmental exposure in field applications. The overmolding of the devices with a clear mold cap or similar material also provides a standoff for optical fibers positioned next to the active facets. The photonic devices are attached to a substrate, which may be flexible that has electronic traces that allow the photonic devices to be connected to an external device such as a semiconductor device. A technique for manufacturing the overmolding cap using a mold die system in combination with a rigid carrier is also disclosed. The rigid carrier is used to maintain the shape of the substrate during the molding process. The proposed method applies to photonic devices used in optoelectronic packages that can serve as transceivers, transmitters, or receivers.

Technique for protecting photonic devices in optoelectronic packages with clear overmolding

Growing community of inventors

San Jose, CA, United States of America

Ken Pham