Preferred Networks, Inc.

Riken Corporation

Ken Namura

Tatsuya Kato

Junichiro Makino

Miyuki Tsubouchi

Takayuki Muranushi

A processing system includes a first chip including one or more first processors, and a second chip including one or more second processors. For a weight of a neural network to be updated, the one or more second processors execute a backward operation of the neural network and calculate a gradient of the weight, the calculated gradient is transferred to the one or more first processors, and the one or more first processors update the weight based on the calculated gradient. The one or more first processors transfer the updated weight to the second chip. The one or more first processors update the weight of the neural network in accordance with a method using multiple types of parameters.

Processing system and processing method for neural network

An integrated circuit for allowing a band of an external memory to be effectively used in processing a layer algorithm is disclosed. One aspect of the present disclosure relates to an integrated circuit including a first arithmetic part including a first arithmetic unit and a first memory, wherein the first arithmetic unit performs an operation and the first memory stores data for use in the first arithmetic unit and a first data transfer control unit that controls transfer of data between the first memory and a second memory of a second arithmetic part including a second arithmetic unit, wherein the second arithmetic part communicates with an external memory via the first arithmetic part.

Integrated circuit, semiconductor device and control method for semiconductor device

A computation device includes: a data multiplexer configured to output first high-order data as first output data and fifth output data, output first low-order data as third output data and seventh output data, output second high-order data as second output data, output second low-order data as fourth output data, output third high-order data, which is high-order data having a second bit number out of third input data, as sixth output data, and output third low-order data, which is low-order data having the second bit number out of the third input data, as eighth output data when a mode signal indicates a second computation mode; and first to fourth multipliers each of which multiplies two output data.

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Tokyo, Japan

Ken Namura