Altera Corporation

S3 Incorporated, Inc.

S3 Graphics Co., Ltd.

Altera Corporaton

Ken Ming Li

Khusrow Kiani

Janusz K Balicki

Behzad Nouban

Chi-Jung Huang

Cameron R McClintock

Bahram Ahanin

James A Watson

Sarathy Sribhashyam

Hiten S Randhawa

Helen Peng

David Hoff

An apparatus for compensating for glitch occurrence in a reset signal that is applied in an integrated circuit, includes: a logic stage capable to process an incoming signal and a delayed incoming signal that is a delayed version of the incoming signal, the logic stage capable to generate an output signal so that when the incoming signal and the delayed incoming signal are in the same state, the output signal will be in the same state. An apparatus for compensating for glitch occurrence in a reset signal that is applied in an integrated circuit, includes: a logic stage capable to process an incoming signal and a delayed incoming signal that is a delayed version of the incoming signal, the logic stage capable to generate an output signal so that when the incoming signal and the delayed incoming signal are in the same state, the output signal will have a state similar to the state of the incoming signal, and when the incoming signal and the delayed incoming signal are not in the same state, the output signal will have a state similar to a previously sampled state of the incoming signal.

Glitch free reset circuit

On-chip resistance, capacitance and/or inductance is implemented in an integrated circuit in vertical configurations using stacked vias and medullization layers within the integrated circuit. Column shaped openings or vias are formed within the integrated circuit and connect from a silicon substrate to various metal traces. The vias are filled with conductive material such as platinum or tungsten. Parallel vias are used to form capacitance, while multiple vias and metal traces are arranged in various patterns over several planes in order to form resistance and/or inductance. The use of the stacked vias and metal traces in a vertical fashion reduces lateral spacing required to implement on-chip resistance, capacitance and/or inductance and allows for more efficient use of space in very large scale integration.

Method for implementing resistance, capacitance and/or inductance in an integrated circuit

A graphics processing system incorporates a calibrator module into the system. As a memory module continuously transmits a model data signal, the calibrator module automatically increments the number of stages of delay, which are integrated into a delayed clock signal. Each delayed clock signal triggers the sampling of the model data signal by a plurality of latches. The calibrator module compares each of these sampled data signals with the original model data signals. If the delayed clock signal is properly aligned with the model data signal to cause the two signals to match, the calibrator module stores a result signal in a '1' logic state. If the delayed clock signal is misaligned with the model data signal, the calibrator module will store the result signal in a '0' logic state. When all of the possible stages of delay have been activated by the calibrator module and the corresponding sampled data signals analyzed, a processor module determines the optimum number of stages of delay needed for proper alignment of the delayed clock signal with the transmitted model data signal

Programmable delay timing calibrator for high speed data interface

A macrocell for use in a programmable logic device (PLD) providing for enhanced logic capability and reduced setup time. The preferred embodiment of the macrocell includes two look-up tables, for increased fan-in, and two flip-flops that increase fan-out, thereby doubling logic capability of the PLD without unacceptably increasing device size. Doubling the register count makes this PLD particularly suitable for applications employing high density sequential logic. Furthermore, a second register can be used for receiving fast input signals form an input to the PLD to reduce setup time.

High speed, low power macrocell

A programmable logic device is presented comprising a global interconnect array whose lines are fed via programmable multiplexers to two stacks of logic array blocks on its sides. The logic array blocks include CMOS look up table based logic modules that consume zero DC power. The global interconnect array lines are fed to the multiplexers in a specific pattern which maximizes routing flexibility and speed. The combination of low power logic array blocks and high performance global interconnect array allows for increased logic density at lower power consumption compared to prior art programmable logic array devices.

PLD with selective inputs from local and global conductors

Macrocell comprised of two look-up tables and two flip-flops

Growing community of inventors

Santa Clara, CA, United States of America

Ken Ming Li