Via Technologies, Inc.

Alpha Imaging Technology Corporation

Ken-Ming Li

Wen-Bo Liu

Vai-Hang Au

Yu-Feng Cheng

Zhen-Yu Song

Zhongding Liu

Joe Bi

Tao Liu

Chun-Fu Lin

Saleh M Abdel-hafeez

Gray Pan

Gary Yang

Yun-Hsiang (Chris) Tsao

Feng-Sheng Chang

Raymond Xu

Chi-Chien Chen

Ke-Fu Ji

Sally Qu

Xiao-Yun Gu

Yongcong Chen

A method for transmitting audio data of a plurality of audio sources through a single SPDIF link, includes: sequencing and multiplexing the audio data of the plurality of audio sources to pack the audio data of the plurality of audio sources into a plurality of frames of a block; performing bi-phase mark encoding on the audio data in the frames; appending preambles Z, X, and Y of the AES3/SPDIF stream format to the frames according to the number of audio sources in a first mode, or appending preambles Z, X, and Y of the AES3/SPDIF stream format and a specific preamble differing from preambles Z, X, and Y to the frames according to the number of audio sources in a second mode; and outputting the frames carrying the audio data into the SPDIF link with a frame rate greater than an audio sampling frequency of one of the audio sources.

Method for transmitting and/or receiving audio data of a plurality of audio sources through a single SPDIF link, and related apparatus

A digital lock detector for a phase-locked loop. The PLL generates a feedback clock according to a reference clock. The digital lock detector includes a match detector and an arbiter. When a first clock transitions, the match detector checks that whether a second clock transitions in a predetermined time window or not. The match detector generates a match signal if the second clock transitions in the predetermined time window. The arbiter counts a number of the successive match signals and generates a lock signal to indicate a lock state when the number exceeds a first predetermined number.

Digital lock detector for phase-locked loop

Dual-function drivers capable of outputting LVDS or TMDS differential signals by sharing output terminals under differential modes. In the dual-function driver, an input control unit receives a first input signal compliant with a first specification in a first mode and a second input signal compliant with a second specification in a second mode by sharing a pair of input terminals, and a current steering circuit comprises first and second differential pairs. The input control unit enables the first and second differential pairs to output a first differential signal compliant with the first specification through a pair of output terminals during the first mode, and the input control unit disables the first differential pair and enables the second differential pair to output a second differential signal compliant with the second specification on the pair of output terminals during the second mode.

Dual-function drivers

A combined transmission unit for TMDS signals and LVDS signals. A first (LVDS) transmission unit comprises a set of first input terminals to receive first data, and a second (TMDS) transmission unit comprises a set of second input terminals to receive second data. A switching controller enables the first transmission unit to transmit the first data to the first external input units through a pair of signal lines coupled to a set of common output line or enables the second transmission unit to transmit the second data to the second external input units through a pair of signal lines coupled to the set of common output line, according to a mode selection signal.

Combined transmitter

A delay locked loop circuit for delaying an input clock to lock a delay clock. The delay locked loop includes a frequency divider for dividing a frequency of the input clock by a number N to obtain a frequency-divided clock, a plurality of delay components for delaying the input clock to generate a plurality of delay clocks with different phase according to a count value, a phase detector coupled to a final delay components for detecting a phase transition between a final delay clock and the input clock, and a counter coupled to the phase detector and the frequency divider for generating the count value according to the phase transition between the final delay clock and the input clock.

Delay locked loop with common counter and method thereof

A power bus for use in an IC is disclosed that is configured as a grid and further formed using strips formed on I/O pads such as data I/O and multi-level voltage I/O pads. An IC is disclosed comprising a power supply I/O pad and a data I/O pad which are made of a deposited conductor. The power supply I/O pad is connected to a power bus and the data I/O pad is connected to circuitry. A strip of deposited conductor is formed closely adjacent to the data I/O pad wherein the strip is connected to the power bus. Parallel paths are developed within the integrated circuit to distribute power within the circuit. A similar approach is taken with respect to multi-level I/O pads. The power bus provide for reduced IR drops and better power supplies to core logic within an integrated circuit.

External power ring with multiple tapings to reduce IR drop in integrated circuit

A LVDS and TMDS dualfunction transmitter for both LVDS and TMDS output channels is disclosed, including an encoder and a serializer. The encoder encodes twenty eight bits of LVDS signals to thirty bits of TMDS signals. The serializer includes four serializer channels for converting the LVDS signals to a serial signal when a LVDS mode is enabled, or converting the TMDS signals to the serial signal when a TMDS mode is enabled. Wherein a first serializer channel is coupled to seven bits of the LVDS signals and outputting a first pair of differential signals. Second, third and fourth serializer channel are coupled to seven bits of the LVDS signals and ten bits of TMDS signals, and outputting a second, third and fourth pair of differential signals, respectively.

LVDS and TMDS dualfunction device

A combined transmission unit for TMDS signals and LVDS signals. First (LVDS) and second (TMDS) transmission units are both coupled to a first set of input terminals. A switching controller, according to a mode selection signal, enables the first transmission unit to transmit the first data on the set of input terminals to first external input units through a pair of first signal lines or enables the second transmission unit to transmit the first data on the set of input terminals to the second external input units through a pair of second signal lines.

A combined output driver for TMDS signals and LVDS signals. First and second output drivers output first and second differential signals to a first external input unit and a second external input unit, respectively, through a pair of signal lines according to first and second input signals. In the second output driver, a driver buffer is coupled to a first voltage and a first node respectively to generate two control signals according to the second input signals. An output unit generates the second differential signal according to the two control signals. A power supply provides a second voltage higher than the first voltage to power the driver buffer and the output unit when the first output driver outputs the first differential signal to the first external input unit.

Combined output driver

A combined output driver for TMDS signals and LVDS signals. A first output driver includes a first differential unit generating a first differential according to first input signals in a first mode and a first clamping device coupled between the first node and the first differential unit to clamp potentials at two power terminals below a second power voltage. The second output driver includes a second differential unit generating a second differential signal according to second input signals in a second mode and a second clamping device to clamp potentials at two output terminals of the second differential unit below the second power voltage.

A combined transmission unit for TMDS signals and LVDS signals. A first (LVDS) transmission unit includes a set of first input terminals to receive first data, and a second (TMDS) transmission unit includes a set of second input terminals to receive second data. A phase locked loop (PLL) generates a first set of output clock signals to the first transmission unit in a first mode and a second set of output clock signals to the second transmission unit in a second mode according to a mode selection signal. The first and second transmission units are able to transmit the first data to the first and second external input units in the first and second modes respectively, according to the mode selection signal and the first and second sets of output clock signals.

Comparators outputting offset calibration. A MOS current mode logic (MCML) circuit receives input signals and generates differential logic signals on output terminals thereof, and comprises a calibration unit coupled to the output terminals, calibrating output offsets at the output terminals according to digital calibration codes. An output stage is coupled to the differential logic signals at the output terminals of the MCML circuit to amplify the differential logic signal and generating a comparison resulting signal. By adjusting the digital calibration codes applied to the calibration unit, current on the output terminals can be adjusted, such that output offsets at the output terminals of the MCML circuitcan be eliminated.

Comparators capable of output offset calibration

A jitter measurement circuit is described comprising delay elements arranged in a serially-connected chain, and first and second sets of circuitry. Each delay elements has an associated delay, an input and an output that produces a delayed version of the signal at the input. The first set of circuitry is configured to detect propagation of the significant instant of the input clock signal through each of the delay elements and produces a pulse in response thereto. The width of the pulse is approximately equal to the delay of the corresponding delay element. The second set of circuitry has one storage element corresponding to each output of the first set of circuitry, for receiving a trigger signal that is timed to correspond to a delay which is approximately half of the total delay of the chain, and for recording in the corresponding storage element any pulse that is active at the time of occurrence of the trigger signal. Thus, a jitter measurement is made based on the pulses recorded in the storage elements after a plurality of trigger signals has occurred.

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Taipei, Taiwan

Ken-Ming Li