Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Ken Mimuro

Mikiya Uchida

Mototaka Ochi

Hiroyuki Doi

Yasushi Okuda

Jun Jisaki

A solid-state image pickup device relating to the present invention has a specific gap in a part of a lattice-shaped light blocking film pattern or wiring pattern having an opening enclosing a light reception region. Peripheral circuits and wiring layers on a pixel may be used as the light blocking film. In such a case, when multiple wiring layers are used as the light blocking film, layouts of a second and subsequent wiring layers is determined according to the layout of the first wiring layer above the light reception region. The specific gap is created in a part of the wiring enclosing the light reception region.

MOS solid-state image pickup device

The semiconductor device of the present invention includes a bootstrap circuit, the bootstrap circuit including: a selection transistor composed of an n-channel MOS transistor; a booster transistor of which a gate is connected to a drain of the selection transistor; and a boosting circuit that is connected between the gate and a source of the booster transistor, and boosts gate voltage with respect to the source of the booster transistor, wherein gate dimensions of the selection transistor are smaller than gate dimensions of the booster transistor. According to this configuration, the semiconductor device can realize increasing an action of a circuit, decreasing a chip size and simplifying processes.

Semiconductor device

A solid-state imaging device including: a plurality of photosensitive cells, each having a photodiode, arranged on a semiconductor substrate () in a matrix; and a peripheral driving circuit that has a plurality of transistors for driving the plurality of photosensitive cells. The plurality of transistors includes a first transistor and a second transistor, the first transistor having a first diffusion layer () as a source or a drain where a signal potential corresponding to a signal charge generated by the photodiode is transmitted and held, and the second transistor having a second diffusion layer as a source and a drain where the signal potential is not transmitted. An edge interval (D) between an edge of a metal silicide layer () formed on a surface of the first diffusion layer and an edge of a gate electrode () in the first transistor is larger than an edge interval between an edge of a metal silicide layer formed on a surface of the second diffusion layer and an edge of a gate electrode in the second transistor. It is possible to suppress a leakage current in the transistors in the peripheral driving circuit, and to hold picked-up image information with high accuracy.

Solid-state imaging device

A solid-state imaging device includes: a plurality of N-type photodiode regions formed inside a P-type well; a gate electrode having one edge being positioned adjacent to each of the photodiode regions; a N-type drain region positioned adjacent to the other edge of the gate electrode; an element-isolating portion having a STI structure, and a gate oxide film having a thickness of not more than 10 nm. One edge of the gate electrode overlaps the photodiode region. First, second and third regions are formed on a surface portion extending from the photodiode region to the drain region, in conditions such that the first region is disposed with a predetermined distance from one edge of the gate electrode and has a P-type first concentration C, the second region is disposed with one edge positioned adjacent to the first region and the other edge overlapping the gate electrode and has a P-type second concentration C, and the third region is disposed with one edge positioned adjacent to the second region and the other edge positioned adjacent to the drain region and has a P-type third concentration C, wherein C&#x3e;C&#x3e;Cor C&#x2248;C&#x3e;C. The readout characteristic at a low voltage is satisfactory, and image defects such as white flaws and dark current are suppressed sufficiently.

Method of manufacturing solid-state imaging device with P-type diffusion layers

Solid-state imaging device and method of manufacturing the same

A method for forming a semiconductor device is provided that allows a desirable semiconductor device to be obtained by preventing a gate electrode of a non-volatile semiconductor memory from having an abnormal shape and the surfaces of high concentration source and drain regions of the non-volatile semiconductor memory from being worn away. The method includes a first step of forming a non-volatile semiconductor memory in a first region of a substrate of the semiconductor device and a second step of forming a semiconductor device in a second region on the substrate. The non-volatile semiconductor memory includes a first gate including a tunnel insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode, and the semiconductor device includes a second gate including a gate insulating film and a gate electrode. In this method, during patterning of the second gate, a surface of the first gate is covered with a protective film that hardly can be etched by an etchant used for the patterning of the second gate.

Growing community of inventors

Toyama, Japan

Ken Mimuro