Renesas Technology Corp.

Hitachi, Ltd.

Renesas Electronics Corporation

Hitachi Ulsi Systems Co., Ltd.

Other

Ken Matsubara

Atsushi Nozoe

Michitaro Kanamitsu

Shoji Kubono

Tetsuya Tsujikawa

Eiji Yamamoto

Yoshinori Takase

Tomoyuki Fujisawa

Keiichi Yoshida

Takashi Iwase

Takayuki Tamura

Takashi Horii

Hideaki Kurata

Shinji Yuasa

Satoru Nakanishi

Takashi Kono

Koichi Takeda

Hidenori Mitani

Hideo Kasai

Makoto Mizuno

Shota Okayama

Akihiko Kanda

Genta Watanabe

Kenji Kawada

Jun Setogawa

Takahiro Shimoi

Tomoya Saito

Fumiko Yamada

Toru Matsushita

A semiconductor device capable of changing a data programming process in a simple manner according to a situation is provided. The semiconductor device includes a plurality of memory cells, a programming circuit for supplying a programming current to the memory cell, and a power supply circuit for supplying power to the programming circuit. The power supply circuit includes a charge pump circuit for boosting the external power supply, a voltage of the external power supply according to the selection indication, and a selectable circuit capable of switching the boosted voltage boosted by the charge pump circuit. The control circuit further includes a control circuit for executing data programming processing by the programming circuit by switching the selection indication.

Semiconductor device and semiconductor system

According to an embodiment, a semiconductor device includes a pre-charge transistor configured to supply a pre-charge voltage to a bit line, a sense amplifier configured to change a logic level of an output signal according to a result of a comparison between a drawing current of a storage element and a reference current, a clamp transistor disposed between the bit line BL and the sense amplifier, and a clamp voltage output transistor, in which a gate of the clamp voltage output transistor is connected to a gate of the clamp transistor, a source of the clamp voltage output transistor is connected to a back gate thereof, the pre-charge voltage is supplied to the source of the clamp voltage output transistor, a drain of the clamp voltage output transistor is connected to the gate thereof, and a ground voltage is supplied to a back gate of the clamp transistor.

Semiconductor device

In order to reduce the manufacturing cost, a flash memory includes a memory cell array formed by a plurality of memory cells arranged in a matrix shape; a plurality of word lines provided in each column of the memory cell array; a first word line driver that outputs a first voltage group to each of the word lines; and a second word line driver that outputs a second voltage group to each of the word lines together with the first word line driver.

Flash memory

Operational stability of the nonvolatile memory in plural power supply voltage modes set up in advance corresponding to the power supply voltage level is realized. A nonvolatile memory is configured with a memory array, a charge pump, a distributor for selecting an output voltage of the charge pump, and a sequencer for controlling operation of the charge pump and the distributor. The nonvolatile memory is also provided with an analyzer which notifies the sequencer of a power supply voltage mode selectively specified among plural power supply voltage modes set up in advance corresponding to power supply voltage levels, and which detects mismatch between the power supply voltage mode notified to the sequencer and an actually supplied power supply voltage and limits the operation of the charge pump and the distributor with the use of the sequencer, based on the detection result. An operational stability of the nonvolatile memory is realized.

Nonvolatile memory, data processing apparatus, and microcomputer application system

A nonvolatile semiconductor memory device is provided which can accurately read data with low consumption current. The flash memory selects a memory cell according to an external address signal in response to the leading edge of a clock signal and reads data from the memory cell in response to the leading edge of the clock signal in the normal read mode, whereas, in the low-speed read mode for performing a read operation with lower power consumption than that of the normal read mode, reads data from the memory cell in response to the trailing edge of the clock signal. Therefore, data can be accurately read even if noise is generated in response to the leading edge of the clock signal in the low-speed read mode, because the noise level has dropped at the trailing edge of the clock signal.

Nonvolatile semiconductor memory device

This invention is to reduce the number of memory gate drivers, while lessening the number of times of disturb occurrence in a memory array configuration that implements writing in small byte units. A memory array comprises a plurality of sub-arrays, MG transfers, SL drivers, and CG drivers. Each sub-array includes a plurality of memory gate lines, control gate lines, source lines, and bit lines. Memory cells are arranged in positions of intersections of these lines. The control gate lines, CG drivers, source lines, and SL drivers are common to the sub-arrays, whereas the memory gate lines and MG buffer circuits are provided for each sub-array. Thereby, the units in which data is written are decreased and adverse effects of disturb are reduced without increasing the circuit size of the memory array.

Semiconductor integrated circuit device

Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls an erase process of performing erasing to the plurality of nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to the nonvolatile memory cell exceeding a pre-write-back level before a depletion level, and a second write process of performing writing to the nonvolatile memory cell exceeding a write-back level after the first write process. Since the occurrence of depletion is suppressed by successively performing the first write process with respect to the nonvolatile memory cells which may exceed the depletion level in the erase process, erasing can be performed to the nonvolatile memory cell without causing depletion halfway therethrough.

Data processing system and nonvolatile memory

A semiconductor storage device which includes a memory array including a plurality of memory cells for storing data by using a difference in a threshold voltage and at least one reference cell for storing data indicative of a state of a corresponding memory cell by using a difference in a threshold voltage, a control circuit for determining a read voltage based on data stored by a reference cell corresponding to a memory cell adjacent to a memory cell to be read, a read unit for executing reading from a memory cell to be read by using a determined read voltage, and a write unit for executing writing, when executing writing to a memory cell to be written to bring the memory cell into a written state, data indicating that the memory cell is in the written state to a reference cell corresponding to the memory cell.

Semiconductor storage device having memory cell for storing data by using difference in threshold voltage

A non-volatile storage device () has non-volatile memory units (FARYto FARY), buffer units (BMRYto BMRY) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.

Non-volatile memory having multiple erase operations

Nonvolatile memory with independent access capability to associated buffer

System for erasing nonvolatile memory

A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order. The method realizes, particularly, (1) suppression of the number of erase verification times to the minimum by performing erase verification only on arbitrary one even-numbered or odd-numbered page in the pages to be erased in consideration of variations in the erasing characteristic, and (2) prevention of erroneous determination of the upper end of erasure since it is unnecessary to set a memory cell to be rewritten every rewrite verification by continuously executing the rewriting process page by page.

Nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array

The disclosed flash memory is provided with a majority logic circuitand shift registersto. Three out of the bankstoof the memory respectively include management information areas KAs to store binary management information comprising power supply trimming data and bitline restoration data. During initialization of the flash memory, the majority logic circuitperforms error correction on management information bits retrieved from the management information areas KAs and outputs that information to a trimming/restoration data buffer, thus providing highly reliable management information very quickly. The shift registerstodelay a control signal that is output from a control circuitby a certain period of time before outputting the control signal to sense amplifiersto. This delay makes it possible to make the operating currents of the bankstostart to flow at different times and to suppress a peak current flowing in the flash memory.

Nonvolatile semiconductor storage device

Growing community of inventors

Higashimurayama, Japan

Ken Matsubara