Intel Corporation

Ken M Crocker

Radhakrishnan Venkataraman

Nicholas D Wade

Randy B Osborne

Nagi Aboulenein

Ram Huggahalli

Vamsee K Madavarapu

A device is presented including a memory controller. The memory controller is connected to a read request queue. A command queue is coupled to the memory controller. A memory page table is connected to the memory controller. The memory page table has many page table entries. A memory page history table is connected to the memory controller. The memory history table has many page history table entries. A pre-calculated lookup table is connected to the memory controller. The memory controller includes a memory scheduling process to reduce memory access latency.

Method and apparatus for memory access scheduling to reduce memory access latency

A method and system for dynamically sizing a dedicated memory in a shared memory buffer architecture. At initial boot, system BIOS programs control register to allocate a dedicated memory of a desired size. The size of the dedicated memory allocated is dependent on the performance requirements. If after initial boot, the performance requirements change, it may necessitate a change in dedicated memory size. By reprogramming the control registers, the dedicated memory size is dynamically changed without any manual manipulation of internal components.

Method and apparatus for dynamically resizing a frame buffer in a shared

Method and apparatus for dynamically allocating and resizing the

A method and system for allowing an arbitrary operating boot in a shared memory buffer architecture system. A chipset including a memory controller, a bridge, and an arbitration unit is used to control access to a shared physical memory. The physical memory is divided between the system memory and dedicated memory to be used by one or more devices. A portion of the physical memory is allocated as a dedicated memory for some system device. The remainder of the memory may be allocated as system memory. The allocation is performed by a system BIOS either at initial start up or through system BIOS calls made during initialization of the device to use the dedicated memory. Programmable bits in the chipset are programmed to prevent the memory controller from claiming dedicated memory accesses during the boot of an operating system. Since the operating system's attempts to write to the dedicated memory are not claimed by the memory controller during memory sizing, they are forwarded to an I/O bus. No 1/0 device claims these addresses, so a memory sizing read back is unanswered, and the operating system is caused to believe the top of memory has been reached below the dedicated memory. If the O/S does not do memory sizing, the system BIOS provides the O/S with the size of system memory available. Thus, in either case, the dedicated memory allocation is transparent to the O/S, and an arbitrary O/S may be employed with the system.

Method and apparatus to permit the boot of a shared memory buffer

Growing community of inventors

Orangevale, CA, United States of America

Ken M Crocker