Vlsi Technology, Inc.

Koninklijke Philips Corporation N.V.

Ken Jaramillo

Carl J Knudsen

Subramanian S Meiyappan

Franklyn H Story

Brian Logsdon

Peter Chambers

David Gerard Spaniol

Prasad Vajjhala

A system and method facilitates simplified debugging of internal component scan testing. In an example embodiment, a TAP controlled internal scan test intermediate debugging system includes an intermediate TAP controller internal scan test system, design circuit blocks, a scan test chain primary input pin, a scan test chain final output pin. The components of the intermediate TAP controlled internal scan test debugging system cooperatively operate to facilitate debugging of faults through extraction of intermediate scan test chain signals. The intermediate TAP controller internal scan test system transmits an indicated intermediate scan test chain signal off of the IC as a TAP test data out (TDO) signal. The intermediate TAP controller internal scan test system utilizes an internal scan observe register to store information indicating which intermediate internal scan test chain signal to forward as a TAP TDO signal.

Test access port (TAP) controller system and method to debug internal intermediate scan test faults

The present invention comprises a smart retry system for agents in a computer system. The smart retry system of the present invention includes a master agent, a slave agent, an arbiter, and smart retry logic components, all adapted to be coupled to a bus. The bus permits agents coupled to the bus to communicate with the arbiter and other agents coupled to the PCI bus. The smart retry logic component of the present invention prevents a PCI master agent from accessing the bus for the purpose of attempting a retry transaction, until after the slave agent that issued the retry is ready.

Smart retry system that reduces wasted bus transactions associated with master retries

A system for preventing bus contention in a multifunction integrated circuit under testing. The system is implemented in an integrated circuit adapted to accept a series of test inputs operable for testing the functionality of the integrated circuit. The integrated circuit includes at least one bus for communicatively coupling the multiple functional blocks. At least a first functional block and a second functional block included in the integrated circuit, the first functional block and the second functional block both coupled to the bus and coupled to accept the test inputs. An output enable controller is also included in the integrated circuit. The output enable controller is coupled to the second functional block and is operable to disable at least one output of the second functional block if a corresponding output of the first functional block is activated. This guarantees that the test inputs can propagate through the first functional block and the second functional block without causing contention for the bus between the first functional block and the second functional block.

Method and system for controlling internal busses to prevent bus contention during internal scan testing

A system for preventing bus contention in a multifunction integrated circuit during testing. The system is implemented in an integrated circuit adapted to accept a series of test inputs operable for testing the functionality of the integrated circuit. The integrated circuit includes at least one bus for communicatively coupling the multiple functional blocks. At least a first functional block and a second functional block included in the integrated circuit, the first functional block and the second functional block both coupled to the bus and coupled to accept the test inputs. A bus arbiter is also included in the integrated circuit for granting ownership of the bus. The bus arbiter is operable to disable at least one output of the second functional block if a corresponding output of the first functional block is activated by using a bus grant signal generated for the first functional block. This guarantees that the test inputs can propagate through the first functional block and the second functional block without causing contention for the bus between the first functional block and the second functional block. Alternatively, a centralized test device controller is used to disable the output of the second functional block, as opposed to using the grant signals of the bus arbiter. This allows the incorporation of the implementing logic without altering the logic of the bus arbiter.

Method and system for controlling internal busses to prevent busses contention during internal scan testing by using a centralized control resource

The present invention is a direct access bridge for translating messages between a first protocol and a second protocol via a first component interface and a second component interface. The first and second component interfaces are adapted to respectively couple to a first and second protocol bus. The first component interface is also coupled to the second component interface. The first component interface is further adapted to transmit and receive data and fundamental message information to and from a first component via the first protocol bus using the first protocol. The second component interface transmits and receives the data and the fundamental message information to and from the second protocol bus in accordance with the second protocol. Similarly, the second component interface and the first component interface transform the data and fundamental message information from the first protocol to the second protocol and vice versa between the first and second bus. The fundamental message information from the second protocol bus to the first protocol bus; and the fundamental message information is provided to a memory coupled to the second protocol bus such that the first component has direct access to the memory. For example, in one embodiment of the present invention a direct access bridge system and method enables a PCI master component to perform a direct memory access read and write of information to a memory associated with an Hitachi SH4 microprocessor using the DDT protocol.

Direct memory access system and method to bridge PCI bus protocols and hitachi SH4 protocols

The present invention comprises a system for implementing pseudo delayed transactions through a bridge in order to guarantee access to a shared device. The system of the present invention functions in a computer system having a plurality of busses, including a first bus on one side of a bridge and a second bus on another side of the bridge. A first initiator device and a second initiator device are coupled to the first bus. The first and second initiator devices are both adapted to request ownership of the first bus and receive a respective first and second grant signal responsive thereto. A target device is coupled to the second bus. The bridge is coupled to the first bus and the second bus. The bridge is adapted to implement data transactions between the target device and the first device or the second device. The bridge is further adapted to support a pseudo delayed transaction for the first or second device, wherein the pseudo delayed transaction is supported without requiring the storage of address or command/byte enable information, such that the first and second device are both guaranteed access to the target device.

Method and system for pseudo delayed transactions through a bridge to guarantee access to a shared resource

A system is delineated comprising, in combination, an integrated circuit having N internal masters coupled to a buried, internal bus, and register circuitry coupled to the buried, internal bus and having an output providing status data for each of the N internal masters. The output from the register circuitry is directly coupled to a processor for permitting the processor to monitor request and grant status for each internal master, thereby allowing the processor to keep track of which, if any, of the internal masters attempt to 'hog' the internal, buried bus. Additionally, the processor can set enabling registers located in the register circuitry to one value for permitting properly operating internal masters to have access to the internal, buried bus, and to another value to disable one or more 'hogging' internal masters from accessing the internal, buried bus. The system further includes N external devices coupled, on a one-to-one basis, to the N internal masters.

System having processor monitoring capability of an integrated circuits

The present invention comprises a priority arbitration system for interfacing a plurality of PCI agents coupled to a peripheral component interconnect (PCI) bus such that high priority PCI agents are satisfied without starving low priority PCI agents. The system of the present includes a PCI bus adapted to transmit data signals. At least one high priority PCI agent is coupled to the PCI bus. At least one low priority PCI agent is coupled to the PCI bus. An arbiter is coupled to the high priority PCI agent and the low priority PCI agent via the PCI bus. The arbiter grants ownership of the PCI bus to the high priority PCI agent prior to granting ownership to the low priority PCI agent. After being granted ownership, the high priority PCI agent becomes an interim low priority PCI agent. The low priority PCI agent is accorded a higher priority by the arbiter than the interim low priority PCI agent. The interim low priority PCI agent reverts to the high priority PCI agent subsequent to a grant to the low priority PCI agent. In this manner, the arbiter, by granting ownership of the PCI bus to the low priority PCI agent before granting ownership of the PCI bus to the interim low priority PCI agent, ensures the low priority PCI agent is not prevented from accessing the PCI bus by the high priority PCI agent.

Priority arbitration system providing low latency and guaranteed access

The present invention comprises a smart retry system for a PCI (peripheral component interconnect) agent in a PCI bus system. The system of the present invention includes an initiator PCI agent and a retry delay register coupled to the initiator PCI agent. The initiator PCI agent is adapted to couple to a PCI bus to communicate with a target PCI agent, via the PCI bus, by initiating a data transaction. The retry delay register is coupled to the PCI agent and the PCI bus. The retry delay register is adapted to receive a delay input via the PCI bus. The delay input describes a latency period of the target PCI agent, wherein the latency period is the amount of the delay. The retry delay register couples the delay input to the initiator PCI agent such that the initiator PCI agent initiates a retry at the expiration of the latency period of the target PCI agent in order to efficiently execute an access to the target PCI agent.

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Phoenix, AZ, United States of America

Ken Jaramillo