Nec Corporation

Renesas Electronics Corporation

Nec Electronics Corporation

Ken Inoue

Tomoko Inoue

Kaoru Mikagi

Masayuki Hamada

Kunihiro Fujii

Kuniko Miyakawa

Makoto Sekine

Shintaro Arai

Nobuaki Hamanaka

Hiroshi Sugawara

Hirohito Watanabe

Hidenobu Miyamoto

Hitoshi Abiko

Minoru Higuchi

Ichirou Honma

A semiconductor device includes a semiconductor substrate including a DRAM portion and a logic portion thereon, an interlayer film covering the DRAM portion and logic portion of the semiconductor substrate, and plural contact plugs formed in the interlayer film in the DRAM portion and the logic portion, the plural contact plugs being in contact with a metal suicide layer on a highly-doped region of source and drain regions of first, second and third transistors in the DRAM portion and the logic portion, an interface between the plural contact plugs and the metal silicide layer being formed at a main surface in the DRAM portion and the logic portion.

Semiconductor device and manufacturing method thereof

In a DRAM-incorporated semiconductor device (SOC) which has a DRAM section and a logic section being formed on one and the same substrate, with the object of providing, with low cost, a SOC having necessary and sufficient characteristics in the DRAM section, while attaining higher-speed performance of the whole elements, silicide is formed at least on all the surfaces of the source-drain regions () and the gate surfaces () of transistors in the DRAM section and the logic section, concurrently in one and the same step.

Semiconductor device having a memory cell section, an adjacent circuit section, and silicide formed on an impurity diffused region

A semiconductor device having a DRAM region and a logic region embedded therein, includes: a substrate having the DRAM region and the logic region respectively formed thereon; a first transistor formed in the DRAM region, and having a first gate insulating film, and a second transistor formed in the logic region, and having a second gate insulating film, wherein equivalent oxide thickness Tof the first gate insulating film of the first transistor is not larger than equivalent oxide thickness Tof the second gate insulating film of the second transistor, the second transistor formed in the logic region has a pocket region which contains an impurity ion having a conductivity type different from that of an impurity ion composing the source/drain regions, while the first transistor formed in the DRAM region has no pocket region.

Semiconductor device where logic region and DRAM are formed on same substrate

A semiconductor device includes a wiring configured to be formed in a surface portion of a first interlayer insulating layer in a first region, a common upper electrode configured to be formed in a surface portion of the first interlayer insulating layer in a second region, a plurality of capacitance portions configured to have the common upper electrode as an upper electrode and be extended below, wherein an upper surface of the first interlayer insulating layer and an upper surface of the common upper electrode approximately lie in the same plane.

A manufacturing method of a semiconductor device includes: forming a wiring in a first interlayer insulating layer in a first region; etching an surface portion of the first interlayer insulating layer in a second region; forming a plurality of opening portions extended below in the etched region; and forming a lower electrode layer, a dielectric layer, and a common upper electrode in each of the plurality of opening portions to form a plurality of capacitance portions. The step of forming the plurality of capacitance portions, includes: forming the common upper electrode so that an upper surface of the first interlayer insulating layer and an upper surface of the common upper electrode approximately lie in the same plane.

Dynamic random access memory with silicide contacts, CMOS logic section and LDD structure

A semiconductor device includes a silicon substrate, a capacitor element having a lower electrode, a capacitor dielectric film, a TiN film, and a W film, and an interlayer insulation film covering the end and a portion of the upper surface of the lower electrode and disposed with a concave portion at a position corresponding to the lower electrode. The lower electrode is disposed selectively at the bottom of the concave portion, the upper surface of the lower electrode is exposed from the interlayer insulation film in the region for forming the concave portion, the side wall for the concave portion of the interlayer insulation film situates to the inner side of the lower electrode from the end of the lower electrode, and the capacitor dielectric film is disposed so as to cover the upper surface of the lower electrode and cover the interlayer insulation from the side wall for the concave portion to the upper surface of the interlayer insulation film.

Semiconductor device having capacitor formed on plug, and method of forming the same

Provided is a semiconductor device which includes a capacitor element having a flat-plate-type lower electrode provided over a semiconductor substrate, a flat-plate-type TiN film provided over the lower electrode in parallel therewith, and a capacitor film provided between the lower electrode and the TiN film; and a first Cu plug brought into contact with the bottom surface of the lower electrode, and is composed of a metal material, wherein the capacitor film has a film which contains an organic molecule as a constituent.

Semiconductor device having capacitor element

In a semiconductor device, a memory region and a logic region are provided on one silicon substrate. A trench is provided in the silicon substrate in the memory region, a memory cell transistor is provided in the memory region and a logic transistor is provided in the logic region. The memory cell transistor includes a first gate electrode constituted by a metal material. The first gate electrode is provided to be buried in the trench and to protrude outside of the trench. The logic transistor includes a second gate electrode constituted by same material as the metal material constituting the first gate electrode.

Semiconductor device including capacitor element and method of manufacturing the same

The present invention provides a semiconductor device comprising: a semiconductor substrate having a DRAM portion and a Logic portion; a first transistor in said DRAM portion; a second transistor in said Logic portion; a first insulating layer covering said DRAM portion and said Logic portion; a first contact plug formed in said first insulating layer in electrically contact with said first transistor in said DRAM portion; a first bit line for said DRAM portion formed on said first insulating layer in electrically contact with said first contact plug; a nitride film formed in contact with said first insulating layer to cover said DRAM portion and said Logic portion, wherein said first bit line locating between said first insulating layer and said nitride film.

Semiconductor device with DRAM portion having capacitor-over-bit-line structure and logic portion

A circuit provides an inhibition to the short circuit between the bit line and the capacitance contact, without employing a self alignment contact (SAC) process. A hard mask is formed on the bit line upper surface and a side wall formed on the side surface of the bit line by etching back a nitride film. A bit contact interlayer film without the SAC structure is etched off except where bit line is formed. A direct nitride film is formed on the entire top and side surface of the bit line so as to cover the bit line in one processing step. Since the upper and side nitride film thicknesses are substantially the same, the height of the bit line can be reduced, enabling further miniaturization. In addition, since the sidewall nitride film is formed without an etch back process, it can more easily be formed with a constant film thickness.

Semiconductor device memory cell

A semiconductor memory device having a transistor formed on a semiconductor substrate and a capacitor formed on the upper layer of the transistor and electrically connected to the transistor, includes: a cell contact which is formed on a first interlayer insulation film covering the transistor and is electrically connected to the transistor; a bit contact which is formed on a second interlayer insulation film provided on the first interlayer insulation film and is electrically connected to the cell contact; a bit line which is formed on the second interlayer insulation film and is connected to the bit contact; a capacitor which is formed on a third interlayer insulation film covering the bit line; a capacitor contact which is formed through the third and second interlayer insulation film and makes a connection between the capacitor and the cell contact; and a side wall which has an etching selectivity with the second and third interlayer insulation films formed on the surface of the bit line.

Semiconductor memory device

The short circuit between the bit line and thee cell contact can be prevented without considerably increasing the number of the manufacturing processes. The bit lineelectrically coupled to the cell contactis formed of the material, which is same as the material of cell contact. In the process for forming the bit lineon the cell contact interlayer filmby etching, the etching for creating an upper surface of the cell contactthat is not coupled to the bit linebeing lower than an upper surface of the cell contactthat is coupled to the bit line. Further, after the formation of the bit line, the barrier metal layerformed on the lower surface of the bit lineis selectively etched.

Semiconductor device having plural electroconductive plugs

The present invention provides an inhibition to the short circuit between the bit line and the capacitance contact, without employing a self alignment contact (SAC) process, in which a hard mask is formed on the upper surface of the bit line and a side wall formed on the side surface of the bit line by etching back a nitride film. A bit contact interlayer film of the conventional semiconductor device which does not have the SAC structure is etched off except the portion where bit line is formed, and then direct nitride film is formed on the entire surface of the top surface and the side surface of the bit line so as to cover the bit line in a same processing step. Since the film thickness of the nitride film disposed on the upper surface of the bit line is designed to be substantially the same as that disposed on the side surface of the nitride film, the height of the bit line itself can be reduced, and thus a further miniaturization becomes possible. In addition, since the nitride film is formed on the side wall of the bit line without requiring an etch back process according to the process of the present invention, the nitride film having a constant film thickness can be easily formed on the side wall of the bit line, as compared with the conventional SAC structure.

A semiconductor memory device having a transistor and a capacitor electrically connected to the transistor, the semiconductor memory device comprising: a first interlayer insulation film covering said transistor; a metallic cell contact passing through said first interlayer insulation film, said cell contact being electrically connected to said transistor; at least one interlayer insulation film located above said first interlayer insulation film; a capacitor located above said first interlayer insulation film; and a capacitor contact passing through said at least one interlayer insulation film, said capacitor contact electrically connecting said capacitor with said cell contact.

Growing community of inventors

Kanagawa, Japan

Ken Inoue