Kabushiki Kaisha Toshiba

Tokyo Shibaura Denki Kabushiki Kaisha

Ken-ichi Maeda

Mitsuo Saito

Takeshi Aikawa

Tsukasa Matoba

Mitsuyoshi Okamura

Yukihito Oowaki

Shinichiro Shiratake

Ryo Fukuda

Takehiro Hasegawa

Shigeyoshi Watanabe

Masako Yoshida

In a semiconductor memory device wherein a plurality of memory cell units formed by connecting a plurality of memory cells in series are provided and each of the memory cell units is connected to a bit line, the semiconductor memory device comprises control circuit for directly reading data of a register cell during a reading operation when the previous row address designates the same memory cell as the present row address, and a data changing controlling circuit for changing data of an arbitrary memory cell of the memory cell unit to data of the memory cell closest to the bit line contact in the memory cell unit, and a row decoder for corresponding row addresses which select the memory of memory cell units, to the upper addresses than the parts of the row addresses which select a memory unit among the memory cell units.

Semiconductor memory device

Each register of an internal register unit of a microprocessor has a pair of register cells consisting of first and second cells having the same register address. When one of these cells is selected, the other cell non-selected serves as a 'back-up cell' for the selected cell. Each register of the register unit has a flag bit for storing a selector flag representing which cell of the pair of cells of the register is currently selected, and a flag bit for storing a change flag representing whether register information of the register is rewritten after a selected cell is changed between the first and second cells of the register. When the register information is stored in one of the pair of cells currently being selected of a certain register and is to be rewritten with another new information, the other cell of the register is selected to store the new information therein. The original register information is held in the first cell, thereby eliminating necessity of saving the original register information to a main memory at this stage. When the original register information is required again, the original register information can be rapidly restored, by only selecting the first cell again, in the corresponding register without executing save/restore processing between the register unit and the main memory.

Device for saving and restoring register information

A cache memory device comprises a data cache memory, an instruction cache memory, an instruction code area change detector, and an instruction code change processor. The instruction code area change detector decides whether writing access to the data cache memory by the processor is to a data area or to an instruction area of a main memory. The instruction code change processor passes the data cache memory to perform direct writing into the main memory when the writing access is to the instruction area, and, when data for a processor address is cached in a tag section of the instruction cache memory, invalidates the effective flag of the tag section.

Cache memory device constituting a memory device used in a computer

A register device includes a register set group, a switching control unit, a write control unit, a write flag memory unit, and a read control unit. The register set group consists of a plurality of register sets each constituted by a plurality of registers. The switching control unit selects a register set to be used in processing from the register set group in response to a saving/recovery instruction. The write control unit writes data in registers of the register set selected by the switching control unit in response to a write instruction. A write flag representing whether data is written in each of the registers is held by the write flag memory unit. The read control unit determines, in response to a read instruction, a register in which data is written most recently of a plurality of registers corresponding to each other between the register sets with reference to the write flags, thereby reading out data from the register.

Register device

Pattern recognition of speech or print input signal patterns is done by deforming the input signal (parameter vector pattern) to generate a set of orthonormal input patterns (basis vectors), the set compared with pre-stored reference vector patterns for similarity and recognition. The vector comparison involves matrix formation and dot-product maximum eigenvalue calculations.

Apparatus and method for recognizing unknown patterns

A character recognition apparatus has an image data generating section for storing image data corresponding to a character array on a sheet of paper and for generating a series of scan line data constituting one item of image data; a segmentation control section for generating starting and end scan line data which define a segment of each character data in accordance with the scan line data sequentially generated from the image data generating section; and a recognizing section for detecting any similarities between the reference character data and the character data generated from the data generating section in accordance with the starting and end scan line data and for generating effective data character data which has the largest similarity which is larger than a predetermined value. When none of the similarities exceed the predetermined value, the recognizing section supplies a control signal to the segmentation control section to update one item of the starting and end scan line data, thereby allowing the image data generating section to generate character data for a different segment.

Character recognition apparatus

A plurality of different mask pattern data which are indicated by values obtained from Hermitte's polynomials of different degrees weighted by a Gaussian function are stored in mask memories, respectively. Each mask pattern data stored in each of the mask memories is convolved by a sum-of-product circuit together with unknown input pattern data. A plurality of extracted pattern feature data are stored in pattern feature memories.

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Kamakura, Japan

Ken-ichi Maeda