Adv Antest Corporation

Agilent Technologies, Inc.

Ken Hanh Duc Lai

Edmundo De La Puente

Alan S Krech, Jr

Xinguo Zhang

Michael Frank Jones

John M Freeseman

Ze'ev Raz

An ATE system performs RA over NAND flash memory DUTs. A first UBM captures fresh failure related data from a DUT. A second UBM transmits existing failure related data. A fail engine accesses the stored existing failure related data and generates a failure list based thereon. The storing and the accessing the existing failure related data, and/or the generating the failure list, are performed in parallel contemporaneously in relation to the capturing the fresh data. The generated failure list is queued. A failure processor, which may be operable for controlling the capturing, computes a redundancy analysis based on the queued failure list. The first and second UBMs then ping-pong operably.

Testing memory devices with parallel processing operations

In one embodiment, an automated test equipment (ATE) system includes a tester having a tester electronics module, an application specific electronics module, and a tester-to-device under test (DUT) interface mount. The tester electronics module has a first electronics interface configured to electrically connect to a tester-to-DUT interface when the tester-to-DUT interface is coupled to the tester-to-DUT interface mount. The application specific electronics module has a second electronics interface and a third electronics interface. The second and third electronics interfaces are configured to electrically connect to the tester-to-DUT interface when the tester-to-DUT interface is coupled to the tester-to-DUT interface mount. The application specific electronics module is configured to communicate with the tester electronics module via the second electronics interface, and with at least one DUT via the third electronics interface.

Tester having an application specific electronics module, and systems and methods that incorporate or use the same

Automated testing system and method of testing memory devices with distributed processing operations. A redundancy analysis system includes multiple test site processors (TSPs) respectively coupled to multiple devices under test (DUTs). Each TSP is installed with a redundancy analyzer configured to analyzing redundancy data returned from a respective (DUT). Each TSP may be coupled with a respective fail engine for returning the redundancy data from the corresponding DUT. A main TSP of the multiple TSPs is configured to control testing routine over the multiple DUTs and process failure related data from the DUTs. The main TSP may direct the RAs distributed in the multiple TSPs to execute the redundancy analyzers in parallel.

Testing memory devices with distributed processing operations

A test program generates transmit vectors (stimuli) and receive vectors (expected responses). The transmit vectors are applied to the DUT, while the receive vectors are treated as comparison values used to decide if a response from the DUT is as expected. While programming a FLASH part the test program uses TAG RAM techniques to maintain a BAD COLUMN table in one of the memory sets. This BAD COLUMN table is addressed by the same address that is applied to the DUT. If an OMIT BAD COLUMN mode is in effect, entries in this table are, by automatic action of the memory tester hardware, obtained and used to supply a replacement programming data value of all 1's that will produce an immediate and automatic indication of successful programming from the DUT. This prevents spending extra time programming a column that has been determined to be bad, without requiring an alteration in the internal mechanism of the test program. The discovery of bad columns and their recordation in the BAD COLUMN table can be performed during an initial programming phase of the test program, or it can be performed on an &ldquo;as-discovered&rdquo; basis during the course of exercising a programmed FLASH DUT. These features may be combined with automatic reading of a special BAD BLOCK table created in interior test memory to facilitate the testing of memory parts that have an internal block structure, by automatically disabling, and removing from further influence on the test program, actions related to a bad block. That bad block may or may not be in a DUT that is being tested in a multi-DUT fashion.

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Sunnyvale, CA, United States of America

Ken Hanh Duc Lai