Nvidia Corporation

Ken Evans

Bhupendra K Ahuja

A phased lock loop (PLL) including a retimer unit, rotator unit, and clock selection unit. The retimer unit is configured for sampling a divided clock generated by a divide-by-N unit with a plurality of phases of an oscillator clock generated by a ring oscillator to generate a plurality of phase shifted divide-by-N clocks. The rotator unit is configured for selectively rotating through the plurality of phase shifted divide-by-N clocks based on a constant phase shift interval, wherein the rotator unit controls a clock selection unit to produce a single output phase selected from a plurality of generated divide-by-N clock phases.

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San Jose, CA, United States of America

Ken Evans