Hrl Laboratories, LLC

Ken Elliott

David H Chow

Peter W Deelman

Susan L Morton

Mark J Rodwell

Rajesh D Rajavel

Stephen Thomas, Iii

A semiconductor device and method are being disclosed. The semiconductor device discloses an InAs layer, a plurality of group III-V ternary layers supported by the InAs layer, and a plurality of group III-V quarternary layers supported by the InAs layer, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer. The method discloses providing an InAs layer, growing a plurality of group III-V ternary layers, and growing a plurality of group III-V quarternary layers, wherein the group III-V ternary layers are separated from each other by a single group III-V quarternary layer and are supported by the InAs layer.

Method and device for growing pseudomorphic A1InAsSb on InAs

Material layer structures that have high mobility, a high conduction band barrier and materials that can be implanted to enable higher performance FET device. The structures contain a quantum well layer disposed between two barriers and disposed above a buffer layer and a substrate.

High performance InAs-based devices

Method and device for growing pseudomorphic AlInAsSb on InAs

Disclosed is a time delay generatorapparatus and method. The apparatus includes a time delay gate, a mixer(a Gilbert cell circuit), and a current digital to analog converter. The mixer, comprised of first and second transistor differential pairsand, receives an analog input signalwithout a delay as well as a delayed input signalproduced by the time gate delay. The digital to analog converter regulates the relative current flow between a first control signaland a second control signal, effectively altering the mixing of the undelayed input signaland the delayed input signalto generate a delayed output signalwith a time or phase delay substantially equal to the temporal delay represented by the digital signal input. The time delay generator exhibits reduced phase noise and a linear time delay response.

Time delay apparatus and method of using same

A sub-micron, on the order of 80-nanometer diameter, resonant tunneling diode having a peak-to-valley ratio of approximately 5.1 to 1, and a method for its manufacture. The invention is unique in that its performance characteristics are unmatched in comparably sized resonant tunneling diodes. Further, the polyimide passivation and planarization methodology provides unexpected processing advantages with respect to application in the fabrication of resonant tunneling diodes. The invention includes a substratethat serves as a foundation for bottom contact layersand a polyimidecoating. An ohmic metal contactand emitter metal contactprotrude above the polyimidecoating exposing the ohmic metal contactand emitter metal contactThe contacts are capped with an etch-resistant coatingthus allowing for the polyimide etch, and other etching processes without adversely affecting the contacts.

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Thousand Oaks, CA, United States of America

Ken Elliott