Intel Corporation

Tahoe Research, Ltd.

Ken Drottar

David Stewart Dunning

Sanjeev S Jahagirdar

Inder M Sodhi

Ryan Donovan Wells

Ashish V Choubal

Rabiul Islam

Vishram Sarurkar

Yun-Han Chen

Satish K Damaraju

Chamath Abhayagunawardhana

Sanjay Dabral

Zale Theodore Schoenborn

Richard S Jensen

Andrew M Volk

Andrew W Martwick

Donald F Cameron

Dave Dunning

Alok Tripathi

Huimin Chen

Hengju Cheng

William T Futral

Darren S Crews

Zeev Offen

Duane G Quiet

Ronald W Swartz

Robert C Glenn

Dennis J Miller

Joseph E Pelissier

Terry L Baucom

Karthisha S Canagasaby

Amir Bashir

Shalini Sharma

Naveed Khan

Vishnu Balraj

Scott T Gardiner

Ryan D Wells

Davied S Dunning

In one embodiment, a processor includes a plurality of domains each to operate at an independently controllable voltage and frequency, a plurality of linear regulators each to receive a first voltage from an off-chip source and controllable to provide a regulated voltage to at least one of the plurality of domains, and a plurality of selectors each coupled to one of the domains, where each selector is configured to provide a regulated voltage from one of the linear regulators or a bypass voltage to a corresponding domain. Other embodiments are described and claimed.

Controlling power delivery to a processor via a bypass

In an embodiment, a processor includes a core to execute instructions, an agent to perform an operation independently of the core, a fabric to couple the core and agent and including a plurality of domains and a logic to receive isochronous parameter information from the agent and environmental information of a platform and to generate first and second values, and a power controller to control a frequency of the domains based at least in part on the first and second values. Other embodiments are described and claimed.

Independently controlling frequency of plurality of power domains in a processor system

A method is provided for transmitting a packet including information describing a bus transaction to be executed at a remote device. A bus transaction is detected on a first bus and a network packet is generated for transmission over a network. The network packet includes an opcode describing the type of bus transaction. One or more control signals of the bus transaction map directly to one or more bits of the opcode to simplify decoding or converting of the bus transaction to the opcode. The packet is transmitted to a remote device and the bus transaction is then replayed at a second bus. In addition, the packet includes a data field having a size that is a multiple of a cache line size. The packet includes separate CRCs for the data and header. The packet also includes a transaction ID to support split transactions over the network. Also, fields in the packet header are provided in a particular order to improve switching efficiency.

Packet format for a distributed system

Disclosed are embodiments of methods and circuits to generate spread spectrum clocks.

Spread spectrum clock generator

A source terminated serial link can recover from a low power mode by turning on multiple current-mode drivers in a phased sequence where the phased sequence is related to a resonant characteristic of a power supply net.

Serial link apparatus, method, and system

In some embodiments an apparatus includes an amplifier, a first inverter having an input coupled to an output of the amplifier, and a second inverter having an input coupled to an output of the first inverter and an output, where the output of the second inverter is fed back to an input of the amplifier. Other embodiments are described and claimed.

Apparatus, amplifier, system and method for receiver equalization

A receiving device within a digital electronic system includes a sampling unit, a voter block, and a local clock phase adjustment unit. The sampling unit samples an input line at three points in time at intervals of one half of a bit period. The sampling unit delivers the values obtained in the sampling process to the voter block. The voter block determines whether to deliver an up or a down vote to the local clock phase adjustment unit. The voter block communicates with the local clock phase adjustment unit via up and down control signals. The local clock phase adjustment unit determines whether the local clock phase should be adjusted, and if so, whether to advance or delay the local clock phase. If certain meta-stable conditions are observed by the voter block, the voter block will vote in one direction in order to push the system out of the meta-stable condition.

Phase/frequency detector for tracking receivers

Apparatus for receiver equalization

Growing community of inventors

Portland, OR, United States of America

Ken Drottar