Intel Corporation

Ken C Haren

Brian M Leitner

Dominic J Gasbarro

Ling Cen

Lee Albion

An end of a queue or a page-crossing within a queue is detected. A virtual memory address for the head of the queue or for the next queue page is pre-translated into a physical memory address while the last entry in the queue or in the current queue page is being serviced.

Method and apparatus for address translation pre-fetch

Data transactions are partitioned to transfer data across a communication connection requiring naturally aligned data transfers of quad-words. It is determining from byte enable signals whether the bytes of the data to be transferred start in the high order dword or end in the low order dword of a quad-word. The transaction is separated into two transactions if the bytes of the data to be transferred start in the high order dword or end in the low order dword of a quad word. A second transaction is created by pre-appending if the bytes of the data to be transferred start in the high order dword. A second transaction is created by post-appending if the bytes of the data to be transferred end in the low order dword of a quad word.

Transaction partitioning

A device, method and computer program for communicating between a device controller and an industry standard bus. This device method and computer program requires no modification of the core logic of the device driver even though the data and commands transmitted between the device controller and the bus require a different format and different length commands. This device utilizes a convert and store logic unit to convert commands from the core unit to a reduced bit format suitable for the industry standard bus.

System and method for conversion of addresses of varying bit lengths between a bus and a device controller

Data is converted from a first granularity to a second granularity different from the first granularity. The ratio &ldquo;n&rdquo; of the second granularity of the data to the first granularity of the data is determined as a power of 2. The least significant n bits of the beginning alignment of the data are added to the least significant n bits of the beginning count of the data, and the carry bit of the sum is designated as &ldquo;c&rdquo;. A logical &ldquo;OR&rdquo; is performed of the bits of the resulting sum to obtain a value designated as &ldquo;d&rdquo;. A number of data units, equal to the sum of &ldquo;c&rdquo; and &ldquo;d&rdquo;, is added to the data.

Data transfer in host expansion bridge

During the boot of a computer system, IRQs from peripheral components located on secondary PCI busses must be transported to the interrupt controller on the compatibility PCI bus for communication to central processing units (CPUs). According to the invention, these IRQs are detected by a Secondary Interrupt Mapping (SIM) device which transports the signals according to a 2 bit bus protocol over a wired-'OR' bus structure to a Primary Interrupt Mapping (PIM) device located on the compatibility PCI bus. The PIM and SIM transport IRQs over the bus structure utilizing a timing sequence and 2-bit bus protocol. The PIM serves as the master device of the timing sequence and at appropriately designated sequence slots receives bus command signals from the SIM which map to particular interrupt signals that the PIM forwards to the interrupt controller on the compatibility PCI bus for transportation to the CPUs.

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Hillsboro, OR, United States of America

Ken C Haren