Matsushita Electric Industrial Co., Ltd.

Ken Arakawa

Seiji Yamahira

Norio Hattori

A nonvolatile semiconductor memory includes a memory cellcomposed of a memory cell transistorhaving a floating gate and a control gate and a memory cell selecting transistor, a reference cellcomposed of a reference cell transistorhaving the same structure as the memory cell transistorand a reference cell selecting transistor, and a reference word line potential generating circuitconnected to a gate of the reference cell selecting transistor, wherein, in a reading operation, the same power supply voltage is applied between a floating gate and a source node of the reference cell transistor, and an intermediate potential between a potential applied when the memory cell selecting transistoris selected and a potential applied when the memory cell selecting transistoris not selected is applied to the gate of the reference cell selecting transistor

Nonvolatile semiconductor memory

Provided are a memory cell array, a column gate array, a row decoder, a column decoder, a sense amplifier array, a read data bus, an output buffer, and a redundancy discrimination signal bus. In the case of redundancy replacement, the output buffer outputs read data excluding the read data of a memory cell block serving as an object of redundancy replacement. In the case of no redundancy replacement, the output buffer outputs read data excluding the read data of a redundant memory cell block. Then, the read data excluded by the output buffer is provided to the output buffer as an output enable signal. The transition timing of the read data excluded by the output buffer is set to be later than that of the other read data.

Semiconductor memory device

A level shift circuit realizes a high-speed and power-saved operation particularly when the input voltage is at a low level. The level shift circuit includes a first gate voltage control circuit controlled by an inverted signal of an input signal, which is inserted between a gate of a third transistor and a second output terminal; a second gate voltage control circuit controlled by the input signal, which is inserted between a gate of a fourth transistor and a first output terminal; a first transistor; and a second transistor. When the input signal shifts from 'H' to 'L', the first transistor turns OFF, the third transistor is turned ON by the first gate voltage control circuit, and then a voltage of the first output terminal rises. The second transistor turns ON, the fourth transistor is turned OFF by the second gate voltage control circuit, and the voltage of the second output terminal goes down.

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Kusatsu, Japan

Ken Arakawa