Advanced Micro Devices Corporation

Spansion LLC.

Fujitsu Corporation

Kelwin Ko

Angela Tai Hui

Yu Nan Sun

Hiroyuki Kinoshita

Hiroyuki Ogawa

Shenqing Fang

Chi K Chang

Wenmei Li

Sameer S Haddad

Richard M Fastow

Jeffrey Allan Shields

Kuo-Tung Chang

Hao Fang

Timothy J Thurgate

Yue-Song He

Narbeh Derhacobian

Kent Kuohua Chang

Masaaki Higashitani

Kazuhiro Mizutani

Maria Chow-Chan

Bill Cox

According to one exemplary embodiment, a floating gate memory cell comprises a stacked gate structure situated on a substrate and situated over a channel region in the substrate. The floating gate memory cell further comprises a recess formed in the substrate adjacent to the stacked gate structure, where the recess has a sidewall, a bottom, and a depth. According to this exemplary embodiment, the floating gate memory cell further comprises a source situated adjacent to the sidewall of the recess and under the stacked gate structure. The floating gate memory cell further comprises a Vss connection region situated under the bottom of the recess and under the source, where the Vss connection region is connected to the source. The Vss connection region being situated under the bottom of the recess causes the source to have a reduced lateral diffusion in the channel region.

Structure and method for low Vss resistance and reduced DIBL in a floating gate memory cell

A method of manufacturing a semiconductor device wherein a final layer of metal is formed on a layer of interlayer dielectric, forming a layer of TiN on the final layer of metal, forming a layer of photoresist on the layer of TiN, patterning and developing the layer of photoresist exposing portions of the final metal layer, and etching the exposed portions of the final metal layer forming metal structures. The layer of photoresist and layer of TiN are removed. A blanket layer of interlayer dielectric is formed on the surface of the semiconductor device. A second layer of photoresist is formed on the blanket layer of interlayer dielectric. The second layer of photoresist is patterned and developed exposing portions of the interlayer dielectric overlying the metal structures. The exposed portions of the interlayer dielectric are etched down to the surface of the metal structures.

Sacrificial TiN arc layer for increased pad etch throughput

A method and system for providing a semiconductor device is described. The semiconductor includes a core and a periphery. The method and system include providing a plurality of core gate stacks in the core, a plurality of sources in the core and a plurality of periphery gate stacks in the periphery. Each of the plurality of core gate stacks includes a first polysilicon gate and a WSi layer above the first polysilicon gate. The plurality of sources resides between a portion of the plurality of core gate stacks. Each of the plurality of periphery gate stacks includes a second polysilicon gate and a CoSi layer on the second polysilicon gate.

Method and system for forming dual gate structures in a nonvolatile memory using a protective layer

A method and system for providing a semiconductor device are described. The semiconductor device includes a substrate, a core and a periphery. The core includes a plurality of core gate stacks having a first plurality of edges, while the periphery a plurality of periphery gate stacks having a second plurality of edges. The method and system include providing a plurality of core spacers, a plurality of periphery spacers, a plurality of core sources and a plurality of conductive regions. The core spacers reside at the first plurality of edges and have a thickness. The periphery spacers reside at the second plurality of edges and have a second thickness greater than the first thickness. The core sources reside between the plurality of core gate stacks. The conductive regions are on the plurality of core sources. This method allows different thicknesses of the spacers to be formed in the core and the periphery so that the spacers can be tailored to the different requirements of the core and periphery.

Method and system for tailoring core and periphery cells in a nonvolatile memory

A method and system for providing a semiconductor device are described. The method and system include providing a plurality of gate stacks and a first source drain halo implant. The first source and drain halo implant uses the plurality of gate stacks as a mask. The method and system also include providing a lightly doped source and drain implant and a N&plus; source and drain implant. The source connection implant is for connecting a portion of the plurality of sources. The second source and drain implant uses the plurality of gate stacks as a mask. Moreover, CoSi formed on the source region provides a lower resistence for lines connecting the sources, allowing a lower dose to be used for the N&plus; source and drain implant.

Method and system for scaling nonvolatile memory cells

The present invention relates to a method of forming a stacked gate flash memory cell and comprises forming a tunnel oxide layer, a first conductive layer, an interpoly dielectric layer, and a second conductive layer in succession over a semiconductor substrate. The method further comprises forming a sacrificial layer over the second conductive layer, and patterning the sacrificial layer to form a sacrificial layer feature having at least one lateral sidewall edge associated therewith. A sidewall spacer is then formed against the lateral sidewall edge of the sacrificial layer, wherein the spacer has a width associated therewith, and the patterned sacrificial layer feature is removed. Finally, the second conductive layer, the interpoly dielectric and the first conductive layer are patterned using the spacer as a hard mask, and defining the stacked gate, wherein a width of the stacked gate is a function of the spacer width.

Innovative narrow gate formation for floating gate flash technology

This invention describes methods for producing gate oxide regions in periphery regions of semiconductor chips, wherein the gate oxide regions have improved electrical properties. The methods involve the deposition of a barrier layer over the periphery of the semiconductor chip to prevent the introduction of contaminating nitrogen atoms into the periphery during a nitridation step in the core region of the semiconductor chip. By preventing the contamination of the gate areas of the periphery, the gate oxide regions so produced have increased breakdown voltages and increased reliability. This invention describes methods for etching the barrier layers used to protect the periphery from tunnel oxide nitridation. Semiconductor devices made with the methods of this invention have longer expected lifetimes and can be manufactured with higher device density.

Barrier layer decreases nitrogen contamination of peripheral gate

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San Jose, CA, United States of America

Kelwin Ko