International Business Machines Corporation

Kelvin Wong

Michael John Palmer

Daniel Frank Moertl

Gerald Mark Grabowski

Peter M Smith

A link interface is provided of a communication protocol using idle flow control digits (flits) to maintain link continuity. The link interface includes: a physical layer of the communication protocol configured to transmit and receive flits via a link, wherein the communication protocol provides for idle flits of first and second sizes for maintaining link continuity, the first size being smaller than the second size; and a data link layer configured to transmit and receive flits to/from the physical layer. The data link layer is configured to remove idle flits of the first size received from the physical layer and to report cyclic redundancy check errors of filtered first sized idle flits in a correct order in relation to other flits.

Efficient error reporting in a link interface

Parity data associated with commands to, and indications from, a configuration register that includes a first command FIFO for receiving commands and a response FIFO for returning indications can be managed. Commands can be tracked by storing the commands in a second command FIFO and a command can be dequeued from the second command FIFO, in response to a command emerging from the response FIFO. Parity data can be generated from the data associated with a write operation, and stored in a parity latch corresponding to the configuration register, in response to the dequeued command being a successfully completed write operation. The generated parity data can be read from a parity latch corresponding to the configuration register and provided the generated parity data for return with an indication that the dequeued command is a successfully completed write operation.

Managing parity data associated with configuration register data

Concepts for a link interface of a communication protocol are presented. Where the communication protocol provides for Idle Flits of first and second sizes for maintaining link continuity, the first size being smaller than the second size, such concepts are configured to remove Idle flits of the first size.

Link interface

Embodiments are directed to a bus bridge transfer protocol in a bus bridge system that uses a tag based transfer protocol to identify transactions. The bus bridge may receive a protocol request from an initiator that does not use the tag based transfer protocol. A designated tag consistent with the tag based transfer protocol may be assigned for use in requests from the non-tag conforming initiator. When receiving a request from the non-tag conforming initiator, an initiator flag is set to indicate that the request is from the non-tag conforming initiator and that the response should be forwarded to the non-tag conforming initiator. When receiving a request from a tag conforming initiator, if the request includes the designated tag, the initiator flag is set to indicate that the response should be forwarded to and that the designated tag is being used in a request from the tag conforming initiator.

Adaptation of a bus bridge transfer protocol

Techniques for reporting defects in a flash memory back-up system include organizing backed-up data into multiple stripes of a logical block address (LBA). A stripe is a set of pages across all available flash memory devices which have the same block and page address. In response to encountering an error in a block of flash memory during back-up of a stripe of data in one or more last pages of a logical block address, the stripe of data is re-written at a page address in the next LBA and preceding LBA metadata is embedded for the stripe of backed-up data in the re-written stripe of data in the next LBA including an indication of the location of new error block in the preceding LBA.

Reporting defects in a flash memory back-up system

A mechanism is provided for loading a phase-locked loop (PLL) configuration into a PLL module using Flash memory. A Flash data image configuration from the Flash memory is loaded into a set of holding registers in response to the PLL module locking a current PLL configuration from a set of current configuration registers. The Flash data image configuration in the set of holding registers is compared to the current PLL configuration in the set of current configuration registers in response to the Flash data image configuration failing to be corrupted. The Flash data image configuration onto a PLL module input in response to the Flash data image configuration differing from the current PLL configuration. The Flash data image configuration is loaded in the set of holding registers into the set of current configuration registers in response to the PLL module locking the Flash data image configuration.

Loading a phase-locked loop (PLL) configuration using flash memory

A method, system, and computer program product are provided for back-up and restoration of data between volatile and flash memory. The method for controlling back-up of data to flash memory includes: organizing back-up data into stripes, wherein a stripe is a set of pages across all available flash memory devices, dies and planes which have the same block and page address; maintaining metadata indicating locations of known bad planes and grown bad planes; using the metadata when writing back-up data to determine which planes to send cache program commands to; and sending cache program commands to three or more stripes of data simultaneously including providing an indication in the stripe that the stripe is handling a cache program command If a grown bad block is encountered whilst saving a stripe of data, the stripe of data is re-written to the next available page address avoiding the grown bad block.

Back-up and restoration of data between volatile and flash memory

A method and system are provided for back-up and restoration of data between volatile and flash memory. The method for controlling back-up of data to flash memory includes: organizing back-up data into stripes, wherein a stripe is a set of pages across all available flash memory devices, dies and planes which have the same block and page address; maintaining metadata indicating locations of known bad planes and grown bad planes; using the metadata when writing back-up data to determine which planes to send cache program commands to; and sending cache program commands to three or more stripes of data simultaneously including providing an indication in the stripe that the stripe is handling a cache program command. If a grown bad block is encountered whilst saving a stripe of data, the stripe of data is re-written to the next available page address avoiding the grown bad block.

A logic circuit comprises a plurality of functional logic units each having an independent clock signal and a trace bus for carrying trace data. A trace gathering logic unit collects trace data from the functional logic units, the trace gathering logic unit having a clock signal independent of the clock signals of the functional logic units and a trace bus for receiving trace data from the functional logic units; multiplexing logic for multiplexing portions of trace data from different functional logic units onto the trace bus of the trace gathering logic unit; and, synchronization logic coupled to the multiplexing logic for communicating trace data from the functional, logic units to the trace gathering logic unit based on the clock signal of the trace gathering logic unit, the synchronization logic comprising detection logic when valid trace data from the functional logic units is available for placing on the trace bus of the trace gathering logic unit, and signaling logic coupled to the detection logic for signaling to the trace gathering logic unit that valid trace data is on the trace bus.

Logic circuit for the gathering of trace data

A mail handler is provided. The mail handler manages a source queue for incoming messages. The source queue has a first count of slots in memory and is associated with a source read pointer and a source write pointer. The mail handler manages the source write pointer and the source read pointer. The mail handler also manages a destination queue for outgoing messages. The destination queue has a second count of slots in memory and is associated with a destination read pointer and a destination write pointer. The mail handler advances the destination write pointer in response to at least one of (i) transferring one or more messages form the source queue to the destination queue and (ii) reserving one or more slots in the destination queue. The at least one processor advances the destination read pointer in response to reading at least one message from the destination queue.

Reserving space in a mail queue

A method and system are provided for back-up and restoration of data between volatile and flash memory. The method for controlling back-up of data to flash memory includes: organizing back-up data into stripes, wherein a stripe is a set of pages across all available flash memory devices, dies and planes which have the same block and page address; maintaining metadata indicating locations of known bad planes and grown bad planes; using the metadata when writing back-up data to determine which planes to send cache program commands to; and sending cache program commands to three or more stripes of data simultaneously including providing an indication in the stripe that the stripe is handling a cache program command. If a grown bad block is encountered while saving a stripe of data, the stripe of data is re-written to the next available page address avoiding the grown bad block.

In one embodiment, a method for back-up of data to flash memory is provided. Backed up data is organized into one or more stripes, wherein a stripe comprises a set of pages across all available flash memory devices which have a same block and page address. Responsive to encountering an error in a block of flash memory during back-up of a particular stripe of data, the particular stripe of data is rewritten starting at a next available page address and excluding a page of flash memory for the block having the error. Subsequent stripes of data in the block having the error are written to pages excluding the page of flash memory for the block having the error.

Back-up of data to flash memory. Data to back up is written into stripes, which are sets of pages across flash memory backup devices having the same block and page address. First metadata is embedded in each stripe indicating any blocks of the flash memory known to be bad. In response to encountering a new error in a block of flash memory during writing data to back up to a stripe, re-writing the stripe starting at the next available stripe excluding pages on the block of flash memory having the new error, writing subsequent stripes excluding pages on the block of flash memory having the new error, and embedding second metadata in the re-written and subsequent stripes indicating the location of the block having the new error. Responsive to finding no bad blocks indicated in the first metadata, initiating a write to two or more stripes simultaneously.

Growing community of inventors

Eastleigh, United Kingdom

Kelvin Wong