Intel Corporation

Kelvin Kwan

Jawad Nasrullah

Vjekoslav Svilan

David Pardo Keppel

David Roger Ditzel

Muhammad M Khellah

Naveen Neelakantam

Christopher B Wilkerson

Jaydeep P Kulkarni

Michael Zelikson

Norbert Unger

Systems and a method for controlling power of a device with power management software are described. In one embodiment, a computer implemented method initiates power control having ON-OFF keying to control power consumption of a device for energy efficiency and energy conservation. An ON-OFF period of the ON-OFF keying for the device is computed. The method sets a target frequency, a target supply voltage, and a power gate control for the device based on the ON-OFF keying.

Method and systems for energy efficiency and energy conservation including on-off keying for power control

A method performed by a multi-core processor is described. The method includes, while a core is executing program code, reading a dirty cache line from the core's last level cache and sending the dirty cache line from the core for storage external from the core, where, the dirty cache line has not been evicted from the cache nor requested by another core or processor.

Apparatus and method for flushing dirty cache lines based on cache activity levels

Systems and methods for entry and exit latency reduction for low power states are described. In one embodiment, a computer implemented method initiates an energy-efficient low power state (e.g., deep sleep state) to reduce power consumption of a device. The method sets a power supply voltage that provides sufficient power to a dual power supply array for retention of states. Logic is powered down in this low power state.

Methods and systems for energy efficiency and energy conservation including entry and exit latency reduction for low power states

In one embodiment, the present invention includes an apparatus having an estimation logic to estimate a dynamic capacitance of a processor circuit of a processor during a plurality of processor cycles, a power gate calculator to calculate a control value for a power gate circuit coupled to a load line and between a voltage regulator and the processor circuit based on the dynamic capacitance estimate, and a controller to control an impedance of the power gate circuit based on the control value. Other embodiments are described and claimed.

Controlling power gate circuitry based on dynamic capacitance of a circuit

Apparatus and method for reduced core entry into a power state having a powered down core cache

A method is described that includes during runtime of a semiconductor die, determining that a next BIST test sequence of a storage component embedded on the die is appropriate. The method further includes applying a BIST test sequence to each valid entry in the storage component. The method also includes marking any newly invalid entries in the storage component as invalid and configuring a respective replacement entry for each of the newly invalid entries.

Growing community of inventors

Santa Clara, CA, United States of America

Kelvin Kwan