Motorola Corporation

Kelvin E McCollough

Jules D Campbell, Jr

Boaz Kochman

Mathew A Rybicki

Jeffrey D Ganger

Geoffrey B Hall

Cheri L Harrington

Colleen M Collins

Javier Saldana

Jeffrey R Hardesty

James John Caserta

Pamela Daniel

A hybrid phase locked loop employs both analog and digital circuitry. A digital to analog converter (DAC) provides a current output signal in conjunction with a current controlled oscillator (ICO). The hybrid phase locked loop employs the digital circuitry, among other reasons, to assist in generating an optimal feedback frequency signal before the loop of the hybrid phase locked loop is closed. The hybrid phase locked loop intelligently employs appropriate switching in strategically placed portions of the hybrid phase locked loop to ensure stable operation once the loop of the hybrid phase locked loop is closed. The hybrid phase locked loop employs baseline components in certain embodiments of the invention. These baseline components are those whose component values may vary significantly as a function of operating conditions, environmental perturbations, and which have relatively relaxed tolerances/precisions. The present implementation of a hybrid phase locked loop, as described in the invention, is capable of operating using a wide variety of components having relaxed tolerances/precisions, including intrinsic devices such as MOSFET capacitors. Such baseline components are employed in electronic devices where low cost is a rigid design constraint; the present invention is appropriate for such low cost applications.

Phase locked loop

In accordance with the present invention, a frequency modulating phase-locked-loop (FMPLL) (,) architecture is implemented. The frequency of the FMPLL (,) is controlled using a current controlled oscillator (ICO) (,). The ICO (,) receives a current signal incorporating feedback to maintain a fixed gain. The ICO (,) associated with the FMPLL (,) establishes a predictable change in the output frequency for a given change in its input controlled current (ICTL). Relying upon this fixed gain, a frequency shift can be created by summing in an additional delta current (IMOD) to the input control current. By periodically varying the magnitude of the current IMOD, a frequency modulated clock is produced at the output of the ICO,. The magnitude of IMOD controls the amount of frequency shift of the frequency modulated clock. By providing an IMOD signal which is proportional to the generated system frequency, a frequency shift proportional to the average, or center, frequency is produced. Therefore, the percentage of frequency modulation is constant regardless of the magnitude of the system clock frequency. By calibrating the output reference of a voltage reference source 146, the desired modulation frequency percent can be further met.

Method and apparatus for a calibrated frequency modulation phase locked loop

A dual bandwidth PLL based clock generation circuit that enables device execution after frequency/phase lock has been safely achieved is provided. A PLL (,) generates a PLL clock output to a divider (,), which divides the PLL clock at a system clock output. A frequency detector (,) detects frequency/phase lock of the PLL and outputs a bandwidth control signal to selectively operate the PLL (,) in a wide or narrow bandwidth mode until the system clock is stabilized to within a predefined bandwidth of a target frequency while the PLL (,) is operating in the narrow bandwidth mode. The frequency detector (,) outputs a frequency lock signal that enables execution in a CPU (,) upon detecting that the PLL (,) has safely locked to a desired output frequency. Thus, the present invention provides a stable system clock for the system prior to the CPU (,) being allowed to begin its operation, thereby substantially avoiding system failures that may result from frequency overshoot of the system clock.

Dual bandwidth phase locked loop frequency lock detection system and method

In accordance with the present invention, a frequency modulating phase-locked-loop (FMPLL) (100) architecture is implemented. The frequency of the FMPLL (100) is controlled using a current controlled oscillator (ICO) (126). The ICO (126) receives a current signal incorporating feedback to maintain a fixed gain. The ICO (126) associated with the FMPLL (100) establishes a predictable change in the output frequency for a given change in its input controlled current (ICTL). Relying upon this fixed gain, a frequency shift can be created by summing in an additional delta current (IMOD) to the input control current. By periodically varying the magnitude of the current IMOD, a frequency modulated clock is produced at the output of the ICO 126. The magnitude of IMOD controls the amount of frequency shift of the frequency modulated clock. By providing an IMOD signal which is proportional to the generated system frequency, a frequency shift proportional to the average, or center, frequency is produced. Therefore, the percentage of frequency modulation is constant regardless of the magnitude of the system clock frequency.

Method and apparatus for a frequency modulation phase locked loop

An integrated circuit (11) has a frequency detection circuit (22) which provides one or more digital signals (50) to a current source (26) based upon a detected frequency of operation of a generated reference clock (48). The signals (50) allows the current source (26) to change its operational state between two or more discrete current output levels in a digitally-controlled manner. Using signals (50), a high current output level can selected and provided by the current source (26) to the external oscillator circuit (16) during a start up mode to ensure that the integrated circuit (11) can start up in an optimally reduced time period. After a start up operation is complete, the signals (50) can then be used to switch the current source (26) into a lower current operational mode whereby electromagnetic interference (EMI) effects are reduced during the normal modes of operation occurring after start up.

Oscillator amplifier with frequency based digital multi-discrete-level

A PLL based clock generation circuit that enables processor execution during phase locking is provided. A PLL (310) generates a PLL clock output to a divider (330), which divides the PLL clock at a system clock output. PLL (310) outputs a frequency lock signal upon acquiring a desired output frequency that initiates a counter (320) and enables execution in a CPU (350) being clocked by the system clock. CPU (350) is thereby enabled to execute during phase locking at a divided frequency without risk of frequency overshoot induced failures. A phase lock signal, indicating PLL (310) has achieved phase lock, output by counter (320) is logically combined (340) with a signal output from CPU (350) requesting maximum frequency operation. The combined signal selects divider (330) to enable a maximum frequency system clock, thereby enabling CPU (350) to execute at maximum frequency when the PLL (310) is safely phase locked.

Fast start-up processor clock generation method and system

Under software control, a loss of clock detect circuit (24) can be enabled to detect loss of clock. A plurality of different clock signals, including the input reference clock (34) to the PLL (12) and the feedback (36) from the PLL (12), are monitored by the loss of clock circuit (24). When the currently selected system clock (38) signal is lost, a control circuit (28) can select an optimal back-up clocking mode based on which clock signals were lost. One such selectable mode is to utilize the input reference clock (34) directly instead of the PLL (12). Another such selectable mode is to utilize the PLL (12) in a self-clocked mode to provide the system clock (38).

Method and apparatus for managing failure of a system clock in a data

The present invention provides a circuit (10) and method for sampling a single-ended signal and then converting the single-ended signal to a differential signal. After the single-ended signal is converted to a differential signal, then the offset voltage and low frequency noise of an operational amplifier (38) are subtracted from the differential signal using analog techniques. The subtraction operation effectively removes an operational amplifier's offset voltage and a low frequency noise from being a source of error in the differential output signal of the circuit.

Differential amplifier circuit having offset cancellation and method

A data processing system (10) includes a programmable clock signal for an analog converter (28). A duty cycle of the programmable clock signal is programmed by an external user in a prescaler rate selection register (16). A counter subsequently counts for a first period of time corresponding to a phase in which the programmable clock signal is asserted. The counter then counts for a second period of time corresponding to a phase in which the programmable clock signal is negated. By allowing the user to program and modify the duty cycle of the programmable clock signal, the performance of the analog converter (28) may be optimized without constraining the requirements of an external system clock.

Programmable clock for an analog converter in a data processor and

A charge-balanced switched-capacitor circuit (50, 61) includes two capacitors (53, 54/72, 73) which are equalized by being connected in parallel during a first time period. This equalization cancels any mismatch in either capacitor (53, 54/72, 73) which would tend to affect an associated common-mode voltage. During a second time period, the two capacitors (53, 54/72, 73) are connected in series between two signal lines (42, 43). In one embodiment, the switched-capacitor circuit (50) forms a common-mode feedback sensing circuit by providing a common-mode feedback voltage to a fully-differential amplifier (41) at a common interconnection point of the two capacitors (53, 54). This embodiment draws no DC current, and thus prevents harmonic distortion of an output signal on the two signal lines when using a slew-rate limited amplifier (41). In another embodiment, the switched-capacitor circuit (61) functions as an input sampler at an input of a switched-capacitor amplifier circuit (60).

Charge-balanced switched-capacitor circuit and amplifier circuit using

A sampling circuit (10, 10') selectively samples, stores and provides multiple output signals with a single amplifier (30). A sampling capacitor (20, 28) is used for each input channel. In order to minimize crosstalk between the multiple channels, each sampling capacitor is selectively electrically isolated from an input of the single amplifier by a switch (18, 25). Each sampling capacitor is further selectively electrically isolated from an output of the single amplifier by another switch (19, 26). A switch structure (50, 52, 54) which is guard ring protected may be used at the input of each channel to further minimize crosstalk errors.

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Austin, TX, United States of America

Kelvin E McCollough