Micron Technology Incorporated

Kelvin Aik Boo Tan

Hong Wan Ng

Seng Kim Ye

See Hiong Leow

Ling Pan

Alaa N Ali

Wen Wei Lum

Implementations described herein relate to various apparatuses and integrated assemblies. In some implementations, an apparatus may include a substrate having a first surface and a second surface that is on an opposite side of the substrate with respect to the first surface. The apparatus may include an integrated circuit disposed on the substrate. The apparatus may include a decoupling capacitor configured to stabilize an input voltage supplied to the integrated circuit, wherein all electrodes of the decoupling capacitor are entirely within a region between the first surface and the second surface.

Capacitor having electrodes formed within a substrate

Methods, systems, and devices for wire bonding for stacked memory dies are described. A memory system may include a stack of memory dies. As the stack grows to include more and more memory dies, the length of the wires coupling the memory dies with the control circuit may increase. Bonding multiple wires using an adhesive may increase a gap between neighboring wires coupled with the same memory die or different memory dies. For example, bonding one wire to a neighboring wire may pull one or both of the bonded wires away from their original placement, increasing a gap between the bonded wires and one or more neighboring wires. Bonding the wires coupled with a lower memory die may increase a gap such that sagging wires coupled with an upper memory die may be positioned in the gap to avoid shorting with the lower wires.

Wire bonding for stacked memory dies

Implementations described herein relate to various semiconductor device assemblies. In some implementations, a semiconductor device assembly includes a first semiconductor die, a second semiconductor die in a stacked arrangement with the first semiconductor die, and a flexible interposer disposed between the first semiconductor die and the second semiconductor die. The flexible interposer may include a first flexible layer, a second flexible layer, and a conductive trace disposed between the first flexible layer and the second flexible layer. A spacer portion of the flexible interposer may space the first semiconductor die from the second semiconductor die. A connecting portion of the flexible interposer may extend from the spacer portion beyond edges of the first semiconductor die and the second semiconductor die.

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Singapore, Singapore

Kelvin Aik Boo Tan