Freescale Semiconductor,inc.

Motorola Corporation

Everspin Technologies, Inc.

Kelly Wayne Kyler

Mark A Durlam

Gregory W Grynkewich

Brian R Butcher

Saied N Tehrani

Nicholas David Rizzo

Eugene Youjun Chen

Gloria J Kerszykowski

Jon Michael Slaughter

Jaynal Abedin Molla

Kenneth H Smith

John J D'Urso

Clarence J Tracy

Mark F Deherrera

Mark DeHerrera

Richard Williams

Bradley Neal Engel

Jaeshin Cho

Theodore Zhu

Jeffrey H Baker

Earl D Fuchs

J Jack Ren

Charles A Synder

Sanjeev Aggarwal

Jonathan K Abrokwah

Peter K Naji

X Theodore Zhu

Steven M Smith

Fred Reece Clayton

Anthony Ciancio

Wayne A Cronin

Craig L Jasper

Charles W Snyder

James H Williams

Michael J Roll

A method of forming a magnetoelectronic device includes forming a dielectric material () surrounding a magnetic bit (), etching the dielectric material () to define an opening () over the magnetic bit () without exposing the magnetic bit (), the opening () having a sidewall, depositing a blanket layer () of cladding material over the dielectric material (), including over the sidewall, removing by a sputtering process the blanket layer () in the bottom of the opening () and the dielectric material () over the magnetic bit (), and forming a conductive material () within the opening () to form a bit line (). This process reduces errors caused by process irregularities such as edges of the bits () protruding and thereby causing defects in the cladding layer () formed thereover. A bit line or digit line so formed may optionally be tapered at the ends () to prevent magnetic reversal of the bit line magnetic moment that otherwise may occur due to external magnetic fields.

Structure and method for fabricating cladded conductive lines in magnetic memories

A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.

Methods for contacting conducting layers overlying magnetoelectronic elements of MRAM devices

A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.

Method of applying cladding material on conductive lines of MRAM devices

A method for fabricating a cladded conductor () for use in a magnetoelectronics device is provided. The method includes providing a substrate () and forming a conductive barrier layer () overlying the substrate (). A dielectric layer () is formed overlying the conductive barrier layer () and a conducting line () is formed within a portion of the dielectric layer (). The dielectric layer () is removed and a flux concentrator () is formed overlying the conducting line ().

Cladded conductor for use in a magnetoelectronics device and method for fabricating the same

Structures for electrical communication with an overlying electrode for a semiconductor element and methods for fabricating such structures are provided. The structure for electrical communication with an overlying electrode comprises a first electrode having a lateral dimension, a semiconductor element overlying the first electrode, and a second electrode overlying the semiconductor element. The second electrode has a lateral dimension that is less than the lateral dimension of the first electrode. A conductive hardmask overlies the second electrode and is in electrical communication with the second electrode. The conductive hardmask has a lateral dimension that is substantially equal to the lateral dimension of the first electrode. A conductive contact element is in electrical communication with the conductive hardmask.

Methods and structures for electrical communication with an overlying electrode for a semiconductor element

Shielded electronic integrated circuit apparatus () includes a substrate (), with an eletronic integrated circuit () formed thereon, and a dielectric region () positioned on the electronic integrated circuit. The dielectric region and the substrate are substantially surrounded by lower and upper magnetic material regions (), deposited using electrochemical deposition, and magnetic material layers on each side (). Each of the lower and upper magnetic material regions preferably include a glue layer (), a seed layer (), and an electrochemically deposited magnetic material layer (). Generally, the electrochemically deposited magnetic material layer can be conveniently deposited by electroplating.

Magnetic shielding for electronic circuits which include magnetic materials

An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element () including a first electrode (), a second electrode () and a spacer layer (). The first electrode () and the second electrode () include ferromagnetic layers (&). A spacer layer () is located between the ferromagnetic layer () of the first electrode () and the ferromagnetic layer () of the second electrode () for permitting tunneling current in a direction generally perpendicular to the ferromagnetic layers (&). The device includes insulative veils () characterized as electrically isolating the first electrode () and the second electrode (), the insulative veils () including non-magnetic and insulating dielectric properties. Additionally disclosed is a method of fabricating the magnetic element () with insulative veils () that have been transformed from having conductive properties to insulative properties through oxygen plasma ashing techniques.

Magnetic element with insulating veils and fabricating method thereof

A method for fabricating a magnetic memory element structure comprises providing a dielectric layer having a conducting via. A first magnetic layer is formed overlying the dielectric layer and is in electrical communication with the conducting via. A non-magnetic layer and a second magnetic layer are formed overlying the first magnetic layer. A first conductive layer is deposited overlying the second magnetic layer and is patterned. A portion of the second magnetic layer is exposed and is transformed to form an inactive portion and an active portion. The active portion comprises a portion of a memory element and the inactive portion comprises an insulator. A sidewall spacer is formed about at least one sidewall of the first conductive layer and a masking tab is formed that overlies a portion of the memory element and extends to overlie at least a portion of the conducting via.

Methods for fabricating MRAM device structures

An improved and novel device and fabrication method for a magnetic element, and more particularly a magnetic element ( ) including a first electrode ( ), a second electrode ( ) and a spacer layer ( ). The first electrode ( ) and the second electrode ( ) include ferromagnetic layers ( & ). A spacer layer ( ) is located between the ferromagnetic layer ( ) of the first electrode ( ) and the ferromagnetic layer ( ) of the second electrode ( ) for permitting tunneling current in a direction generally perpendicular to the ferromagnetic layers ( & ). The device includes insulative veils ( ) characterized as electrically isolating the first electrode ( ) and the second electrode ( ), the insulative veils ( ) including non-magnetic and insulating dielectric properties. Additionally disclosed is a method of fabricating the magnetic element ( ) with insulative veils ( ) that have been transformed from having conductive properties to insulative properties through oxygen plasma ashing techniques.

Method of fabricating a magnetic element with insulating veils

A method of fabricating a magnetoresistive random access memory device comprising the steps of providing a substrate, forming a conductive layer positioned on the substrate, forming a magnetoresistive random access memory device positioned on conductive layer, forming a metal cap on the magnetoresistive random access memory device, and electroless plating a bump metal layer on the metal cap. The bump metal layer acts as a self-aligned via for a bit line subsequently formed thereon.

Method of fabricating a self-aligned via contact for a magnetic memory element

A method of fabricating a magnetoresistive random access memory device comprising the steps of providing a substrate, forming a first conductive layer positioned on the substrate, forming a conductive material stack region with a flat surface, the conductive material stack region being positioned on a portion of the first conductive layer, and forming a magnetoresistive random access memory device positioned on the flat surface of the conductive material stack region, the magnetoresistive random access memory device being isolated from the first conductive layer and subsequent layers grown thereon.

Method of fabricating a self-aligned magnetic tunneling junction and via contact

A method of fabricating a MRAM device with a taper comprising the steps of providing a substrate, forming a dielectric region with positioned on the substrate, patterning and isotropically etching through the dielectric region to the substrate to form a trench, depositing the MRAM device within the trench wherein the MRAM device includes a first ferromagnetic region with a width positioned on the substrate, a non-ferromagnetic spacer layer with a width positioned on the first ferromagnetic region, and a second ferromagnetic region with a width positioned on the non-ferromagnetic spacer layer wherein the taper is formed by making the width of the first ferromagnetic region greater than the width of the non-ferromagnetic spacer layer, and the width of the non-ferromagnetic spacer layer greater than the width of the second ferromagnetic region so that the first ferromagnetic region is separated from the second ferromagnetic region.

Magnetoresistive random access memory device and method of fabrication thereof

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Mesa, AZ, United States of America

Kelly Wayne Kyler