Hewlett-Packard Development Company, L.p.

Kelly Larson

Robert D Bushey

A system and method of evaluating cache coherency protocols and algorithms in scalable symmetric multiple processor computer systems. The system includes scalable 32-byte or larger cache lines wherein one specific byte in the cache line is assigned for write and read transactions for each specific 32-bit processor. The method includes steps to ensure each 32-bit processor writes and reads to and from the specific byte in the cache line assigned to that 32-bit processor.

Growing community of inventors

Austin, TX, United States of America

Kelly Larson