Agere Systems Inc.

Maxtor Corporation

Lsi Corporation

Quantum Corporation

Avago Technologies General IP (Singapore) Pte. Ltd.

Stmicroelectronics S.r.l.

Kelly K Fitzpatrick

Weijun Tan

Shaohua Yang

Erich Franz Haratsch

Peter A McEwen

Hao Zhong

Jonathan James Ashley

Bahjat Zafer

Yuan Xing Lee

George Mathew

Ara Patapoutian

Zongwang Li

Kevin Dean Fisher

John J McEwen, Legal Representative

Bahjat Zafar

Cory Modlin

Fan Zhang

Bruce Alexander Wilson

Hongwei Song

Jeffrey Lee Sonntag

Richard Rauschmayer

Ke Han

Wu Chang

Changyou Xu

Xuebin Wu

Angelo Dati

Seongwook Jeong

Pierandrea Savo

Necip Sayiner

Harley Burger

Han Fang

Pauline Bolte

Steve Aronson

Ezio Iacazio

Steve Stupp

Hossein Sedarat

Systems and methods relating generally to data storage, and more particularly to systems and methods for encoding to modify the size of an information set.

Systems and methods for high throughput multi-input compression

A data detector includes a branch metric calculator operable to calculate branch metrics for transitions between states in a trellis for the data detector, and a pruning circuit operable to prune prohibited states from the trellis. The states in the trellis comprise basic states and extended states, where the extended states have a greater number of bits than the basic states.

Data detector with extended states

Methods and apparatus are provided for high-speed, low-power, high-performance channel detection. A soft-output detector is provided for processing a received signal, comprising: a forward detector for calculating forward state metrics; a backward detector for calculating backward state metrics; and a current branch detector for calculating a current branch metric, wherein at least two of the forward detector, the backward detector and the current branch detector employ trellis structures with a different number of states. A method is provided for processing a received signal using a soft-output detector, comprising: calculating forward state metrics using a forward detector; calculating backward state metrics using a backward detector; and calculating a current branch metric using a current branch detector, wherein at least two of the forward detector, the backward detector and the current branch detector employ trellis structures with a different number of states.

Methods and apparatus for map detection with reduced complexity

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for data processing systems with symbol selective scaling interacting with parity forcing.

Symbol selective scaling with parity forcing

Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit having a data detection circuit is disclosed that includes: a scaling circuit, a soft output calculation circuit, and a factor calculation circuit. The scaling circuit is operable to scale a branch metric value by a scaling factor to yield a scaled output. The soft output calculation circuit is operable to calculate a soft output based at least in part on the scaled output. The factor calculation circuit operable to modify the scaling factor based at least in part on the soft output.

Systems and methods for auto scaling in a data processing system

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes a decoder circuit providing a decoded output, and a dynamic scalar calculation circuit that determines a first dynamic scaling value and a second dynamic scaling value based at least in part on the decoded output. A first multiplier circuit multiplies the decoded output by the first dynamic scaling value and provides a first scaled output. A detector circuit receives the first scaled output and provides a detected output. A second multiplier circuit multiplies the detected output by the second dynamic scaling value and provides a second scaled output.

Systems and methods for dynamic scaling in a read data processing system

Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is discussed that includes: a noise predictive filter circuit, a mean calculation circuit, a summation circuit, and a filter tap adaptation circuit. The noise predictive filter circuit is operable to perform a noise predictive filtering process on a data input based upon a selector input to yield a noise predictive output. The selector input is derived from a data detector output. The mean calculation circuit is operable to average two or more instances of the noise predictive output to yield a mean output. The summation circuit is operable to subtract the mean output from the noise predictive output to yield a sum output. The filter tap adaptation circuit is operable to adaptively calculate a filter tap based at least in part on a value derived from the data input and a value derived from the sum output.

Systems and methods for area efficient noise predictive filter calibration

Methods and apparatus are provided for high-speed, low-power, high-performance channel detection. A soft output channel detector is provided that operates at a rate of 1/N and detects N bits per 1/N-rate clock cycle. The channel detector comprises a plurality, D, of MAP detectors operating in parallel, wherein each of the MAP detectors generates N/D log-likelihood ratio values per 1/N-rate clock cycle and wherein at least one of the plurality of MAP detectors constrains each of the bits. The log-likelihood ratio values can be merged to form an output sequence. A single MAP detector is also provided that comprises a forward detector for calculating forward state metrics; a backward detector for calculating backward state metrics; and a current branch detector for calculating a current branch metric, wherein at least two of the forward detector, the backward detector and the current branch detector employ different trellis structures.

A reliability unit is provided for determining a reliability value for at least one bit decision. The disclosed reliability unit comprises one or more functional elements, wherein each of the functional elements comprises at least four functional units and at least two registers, wherein each functional unit comprises a comparator and a multiplexer, and wherein an output of the comparator and an equivalence bit control the multiplexer. Generally, the reliability unit determines a reliability value for a bit decision associated with a maximum-likelihood path through a multiple-step trellis.

Reliability unit for determining a reliability value for at least one bit decision

Various embodiments of the present invention provide systems and methods for data regeneration. For example, a system for regenerating data is disclosed. The system includes a media defect detector that is operable to identify a potential media defect associated with a medium from which an input signal is derived, an attenuation amplitude detector that generates an attenuation factor, and a data detector. The data detector includes a first data path and a second data path. The first data path includes a bank of two or more selectable noise prediction filters and the second data path includes a fixed noise prediction filter and the attenuation factor. The data detector processes a derivative of the input signal using the second data path when the potential media defect is indicated, and processes the derivative of the input signal using the first data path when a media defect is not indicated.

Systems and methods for recovering information from a defective medium

Methods and apparatus are provided for performing SOVA detection at higher data rates than achievable with conventional designs. A received signal is processed by (i) determining at least three selection signals that define a plurality of paths through a multiple-step trellis into a given state, wherein a first of the plurality of paths is a winning path for each single-step-trellis period of a multiple-step-trellis cycle, a second path is a winning path for a first single-step-trellis period and is a losing path for a second single-step-trellis period of a multiple-step-trellis cycle and a third path is a losing path for a first single-step-trellis period and is a winning path for a second single-step-trellis period of a multiple-step-trellis cycle; and (ii) determining at least one reliability value (such as a reliability value for a bit decision associated with a maximum-likelihood path through the multiple-step trellis or a plurality of reliability values for each multiple-step-trellis cycle).

Methods and apparatus for processing a received signal using a multiple-step trellis and selection signals for multiple trellis paths

A path comparison unit is disclosed for determining paths in a trellis that compete with a survivor path. The disclosed path comparison unit comprises a first type functional unit comprising a multiplexer and a register to store one or more survivor bits associated with the survivor path; and at least two second type functional units, wherein each second type functional unit comprises a multiplexer and a logical circuit to compute at least one equivalence bit indicating whether the bit for a respective path and the bit for the survivor path are equivalent. Generally, the respective path is one or more of a win-lose path and a lose-win path.

Path comparison unit for determining paths in a trellis that compete with a survivor path

Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing circuit is disclosed that includes a first data detection circuit that applies a phase dependent data detection algorithm to a data set such that a first output of the first data detection circuit varies depending upon a phase of the data set presented to the first data detection circuit. A first phase of the data set is presented to the first data detection circuit. The circuits further include a decoder circuit that applies a decoding algorithm to the first output to yield a decoded output, and a phase shift circuit that phase shifts the decoded output such that a second phase of the data set is provided as a phase shifted output. A second detection circuit applies a phase dependent data detection algorithm to the phase shifted output such that a second output of the second data detection circuit varies from the first output at least in part due to a different phase of the data set presented to the second data detection circuit.

Systems and methods for phase dependent data detection in iterative decoding

Various embodiments of the present invention provide systems and methods for data regeneration. For example, a system for data regeneration is disclosed that includes a data input derived from the medium. A data detector and a data recovery system receive the data input. The data detector provides a first soft output, and the data recovery system provides a second soft output. The first soft output and the second soft output are provided to a multiplexer. A media defect detector performs a media defect detection process, and provides a defect flag that indicates whether the data input is derived from a defective portion of the medium. The defect flag is provided to the multiplexer where it is used to select whether the first soft output or the second soft output is provides as an extrinsic output.

Systems and methods for using intrinsic data for regenerating data from a defective medium

Various embodiments of the present invention provide systems and methods for data regeneration. For example, a method for data regeneration is disclosed that includes receiving a data input derived from a medium, determining a media defect corresponding to the data input, and determining an attenuation factor associated with the defective medium. Based at least in part on the determination that the medium is defective, amplifying the data input by a derivative of the attenuation factor to regenerate the data.

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Sudbury, MA, United States of America

Kelly K Fitzpatrick