Intel Corporation

Kelly J Fitzpatrick

Keng L Wong

Jeffrey E Smith

Goutam Debnath

An integrated circuit and a process for manufacturing the same wherein the integrated circuit includes a substrate, a first insulative layer disposed on the substrate, and a first conductive layer disposed on the first insulative layer, the first conductive layer having a plurality of conductive channels arranged into horizontal tracks. The plurality of conductive channels are for providing two power sources V.sub.SS and V.sub.CC to cells (e.g. standard cells in control blocks) in the integrated circuit. A second insulative layer is disposed on the first conductive layer, and a second conductive layer is disposed on the second insulative layer, the second conductive layer arranged into a plurality of vertical tracks, each of the plurality of vertical tracks are broken into a plurality of segments. Each of the plurality of segments are for carrying one of the power sources, V.sub.SS and V.sub.CC to the cells in the integrated circuit, each of the plurality of segments coupled to a corresponding channel in the first conductive layer through first vias in the second insulative layer. The integrated circuit may also have a third insulative layer disposed on the second conductive layer, and a third conductive layer disposed on the third insulative layer, the third conductive layer providing interconnection of the segments in each of the vertical tracks through second vias in the third insulative layer, the interconnection provided by horizontal tracks in the third conductive layer. In implemented embodiments, the breaking of the vertical power tracks in the second conductive layer into segments for supplying power to the cells results in a net decrease in the area consumed by power buses in the cells, and thus, more area is available for non-power signal lines. The overall area of the integrated circuit may be thereby reduced.

Power bus for an integrated circuit including end-to-end arranged

A clock distribution system and clock interrupt system for an integrated circuit device. Ignoring effects associated with the matched stages, the present invention includes a clock distribution and interrupt system for providing clock signals with less than 100 picoseconds of skew to various components of an integrated circuit device. The present invention utilizes several stages of drivers to evenly supply the distributed clock signals and each stage has RC matched input lines. The present invention advantageously locates the matched stages and clock drivers within the power supply ring of the integrated circuit located on the periphery of the microprocessor topology. This is done in order to better predict the topology surrounding these lines to match the capacitance of these lines. Further, this metal level offers a larger width dimension line (since as a top layer it may be thicker) having less resistance per unit area and also generally avoids spatial competition with other IC components and circuitry. The present invention additionally offers the capability of selectively powering down various components within the integrated device with a power management unit and enable network that is included as a component of the clock distribution system.

Method and apparatus for power management of an integrated circuit

Method and apparatus supplying synchronous clock signals to circuit

A method and apparatus for inserting clock buffers to reduce clock skew in a logic block in which the proper placement of the cells within the logic block is first determined. Given this cell placement and the location of the local clock lines, the placement of clock buffers within the logic block is determined such that the clock buffers are in close proximity to the local clock lines. Routing is then performed to connect the clock buffers to their corresponding clock trunks and the cells requiring clock signals to their corresponding clock buffers. The performance of the logic block is then evaluated. If the performance does not satisfy a predetermined minimum threshold then the cells are modified to satisfy the minimum threshold, or come closer to attaining it. The clock buffers are removed, and the proper placement of the new cells within the logic block is determined. Given this new cell placement a new set of clock buffers is placed and a new routing is created. The performance is then re-evaluated and, if the minimum threshold still has not been attained, the above process is repeated.

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Beaverton, OR, United States of America

Kelly J Fitzpatrick