International Business Machines Corporation

Kelly A Ockunzzi

Mark R Taylor

Richard J Grupp

Michael Richard Ouellette

Kevin William Gorman

Michael Thomas Fragano

Bruce Cowan

Aaron J Cummings

Jessica H Pratt

Aspects of the invention provide a bypass structure for a memory device for reducing unknown test values, and a related method. In one embodiment, a bypass structure for a memory device is disclosed. The bypass structure includes: a logic gate configured to receive a test signal and a clock signal; and an output latch configured to receive an output of the logic gate, an output of the memory device, and a bypass data signal, wherein the output latch is configured to hold the bypass data signal and bypass the output of the memory device in response to asserting the test signal, such that unknown data from the output of the memory device is bypassed.

Bypass structure for a memory device and method to reduce unknown test values

Novel structures and testing methods for the FPGAs (Field-Programmable Gate Arrays) embedded in an ASIC (Application-Specific Integrated Circuits). Basically, a shift/interface system is coupled between the FPGAs and the ASIC. During normal operation, the shift/interface system electrically couples the FPGAs to the ASIC. During the testing of the FPGAs, the shift/interface system scans in FPGA test data in series, then feeds the FPGA test data to the FPGAs, then receives FPGA response data from the FPGAs, and then scans out the FPGA response data in series. During the testing of the ASIC, the shift/interface system scans in ASIC test data in series, then feeds the ASIC test data to the ASIC, then receives ASIC response data from the ASIC, and then scans out the ASIC response data in series.

Mechanism to provide test access to third-party macro circuits embedded in an ASIC (application-specific integrated circuit)

Novel structures and testing methods for the FPGAs (Field-Programmable Gate Arrays) embedded in an ASIC (Application-Specific Integrated Circuit). Basically, a shift/interface system is coupled between the FPGAs and the ASIC. During normal operation, the shift/interface system electrically couples the FPGAs to the ASIC. During the testing of the FPGAs, the shift/interface system scans in FPGA test data in series, then feeds the FPGA test data to the FPGAs, then receives FPGA response data from the FPGAs, and then scans out the FPGA response data in series. During the testing of the ASIC, the shift/interface system scans in ASIC test data in series, then feeds the ASIC test data to the ASIC, then receives ASIC response data from the ASIC, and then scans out the ASIC response data in series.

A structure and associated method for associated grouping of an alpha device with a plurality of dependent devices for a manufacturing test. The alpha device comprises at least one electrical characteristic. The plurality of dependent devices each comprise the at least one electrical characteristic. The alpha device and the plurality dependent devices are grouped together within a semiconductor device for an associated manufacturing test.

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Essex Junction, VT, United States of America

Kelly A Ockunzzi