Altera Corporation

Kellie Marks

Kulwinder Singh Dhanoa

Lei Xu

Michael Philip Fitton

Benjamin Thomas Cope

Martin Langhammer

Steven Perry

Volker Mauer

Suleyman Sirri Demirsoy

Zhengjun Pan

Martin Roberts

Systems and methods are disclosed for interfacing between hard logic elements and soft logic elements implemented on an integrated device. In particular, a configurable interface is provided that includes interconnects between hard logic and soft logic, which enable signals to be selectively routed between the inputs and outputs of hard logic blocks and soft logic modules. The interconnects allow for certain hard logic blocks to be bypassed in favor of soft logic functionality. Moreover, the interconnects allow soft logic to augment the processing of hard logic blocks, e.g., by providing additional signals to the hard logic block.

Systems and methods for interfacing between hard logic and soft logic in a hybrid integrated device

Data signal items output by a radix 42fast Fourier transform ('FFT') operation may not be in the order desired for further use of those data items (e.g., they may be output in a non-natural order rather than in a desired natural order). Memory circuitry (e.g., dual-port memory circuitry) may be used in conjunction with circuitry for addressing the memory circuitry with address signals that are reordered in a particular way for each successive set of N data items. This allows use of memory circuitry with fewer data item storage locations than would otherwise be required to reorder the data items from non-natural to natural order. In particular, the memory circuitry only needs to be able to store N data items at any one time, which is more efficient memory utilization than would otherwise be possible.

Methods and apparatus for reordering data signals in fast fourier transform systems

Interleaving in which functions relating final and original positions are implemented with low complexity using inequalities based on the functions.

Data resequencing

In the provided architecture, one or more multi-threaded processors may be combined with hardware blocks having increased functionality. Each hardware block may be able to transfer a data packet to a particular hardware block based on the packet being processing. One or more hardware block may also be able to divide packets into subpackets for separate processing, and other hardware blocks may be able to rejoin the subpackets. Hardware blocks may also be able to transfer packet information between other hardware blocks during the processing sequence.

Software based data flows addressing hardware block based processing requirements

Growing community of inventors

Lane End, United Kingdom

Kellie Marks