Spansion Llc.

Fasl LLC

Kelley Kyle Higgins

Ibrahim K Burki

Joseph William Wiseman

Robert Louis Dawson

Shengnian Davis Song

A method of forming an integrated circuit includes providing a semiconductor substrate and forming a gate over the semiconductor substrate. A gate sidewall spacer is formed around the gate and a resist is deposited on the gate sidewall spacer with the gate sidewall spacer and the gate exposed. A portion of the gate within the gate sidewall spacer is removed and a gate silicide is formed within the curved gate sidewall spacer. A dielectric layer is formed over the gate silicide and a contact is formed to the gate silicide.

Method for containing a silicided gate within a sidewall spacer in integrated circuit technology

A method for manufacturing a semiconductor component using a sacrificial masking structure. A semiconductor device is formed from a semiconductor substrate and a layer of dielectric material is formed over the semiconductor substrate and the semiconductor device. The layer of dielectric material may be formed directly on the semiconductor substrate or spaced apart from the semiconductor substrate by an interlayer. Posts or protrusions having sidewalls are formed from the layer of dielectric material. An electrically insulating material that is preferably different from the layer of dielectric material is formed adjacent the sidewalls of the posts. The electrically insulating material is planarized and the posts are removed to form openings that may expose a portion of the semiconductor device or a portion of the interlayer material. An electrically conductive material is formed in the openings.

Method for manufacturing a semiconductor component

Methods and structures are provided for a dual-bit EEPROM semiconductor device. The dual-bit memory device comprises a semiconductor substrate, a tunnel oxide disposed on the semiconductor substrate and first and second spaced apart floating gates that are disposed on the tunnel oxide. An interlayer dielectric layer contacts the tunnel oxide layer at a position between the first and second spaced apart floating gates and electrically isolates the first and second spaced apart floating gates. A control gate contacts the interlayer dielectric layer between the first and second spaced apart floating gates.

Semiconductor memory devices and methods for fabricating the same

A semiconductor component having a substantially planar surface on which a film can be deposited and a method for manufacturing the semiconductor component. A layer of dielectric material is formed over a semiconductor substrate and a layer of polysilicon is formed on the layer of dielectric material. The polysilicon layer is patterned to form floating gate structures and expose portions of the layer of dielectric material. Additional dielectric material is formed over the floating gate structures and the exposed portions of the layer of dielectric material. The additional dielectric material is planarized such that it has a surface that is substantially contiguous with and coplanar with the floating gate structures. An oxide-nitride-oxide (ONO) dielectric structure or stack is formed on the surfaces of the floating gate structures and the dielectric material. A layer of polysilicon is formed on the ONO dielectric structure.

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Austin, TX, United States of America

Kelley Kyle Higgins