Boe Technology Group Co., Ltd.

Chongqing Boe Optoelectronics Technology Co., Ltd.

Keke Gu

Zhijian Qi

Xin Peng Liu

Zhe Li

Peng Li

Shuai Chen

Ni Yang

Xiaoji Li

Zhi Zhang

Wei Hu

Jaikwang Kim

Shaoru Li

Lijun Xiao

Lan Xin

Haoxiang Fan

Junhong Lu

Yusong Hou

Hui Li

Xu Lu

Zhihui Wang

Taoliang Tang

Peng Qin

Mengjie Wang

Wei Zhu

Qian Qian

Siqing Fu

Yi Dan

Lisheng Liang

Wenliang Liu

Wenlong Feng

Daoping Yu

Xiaochen Cui

Zhidan Sun

Guanyu Zhou

Zhongping Gou

An array substrate and a display device including the array substrate are provided. The array substrate includes: an upper electrode layer on a base substrate and including a first upper electrode strip and a second upper electrode strip; a lower electrode layer between the base substrate and the upper electrode layer. The lower electrode layer includes a portion that does not overlap the first upper electrode strip and the second upper electrode strip in a direction perpendicular to an upper surface of the base substrate. The array substrate includes a pixel electrode strip and a common electrode strip which are in a same layer and both correspond to a region between the first upper electrode strip and the second upper electrode strip.

Array substrate and display device

An array substrate, a method for manufacturing the same, a liquid crystal display panel, and a display device are provided. The array substrate includes a first substrate, signal lines and an insulating layer; the insulating layer is disposed on the first substrate, and grooves are disposed on a side of the insulating layer facing away from the first substrate and disposed in a region of the insulating layer corresponding to a non-display region of the array substrate; and the signal lines are disposed on inner walls of the grooves, a direction of the inner walls of the grooves is arranged such that at least a portion of light incident on the signal lines from a side of the first substrate facing away from the signal lines is reflected to a display region of the array substrate.

Array substrate and method for manufacturing the same, liquid crystal display panel, display device

A thin film transistor includes a gate, an active layer, a source, a drain. The source includes a connecting portion, a first sub-portion, a second sub-portion, and a third sub-portion that are arranged sequentially and in parallel. At first ends of the sub-portions, the connecting portion is connected to the portions to form two adjacent recesses. At second ends of the sub-portions, the distance from an end of the second sub-portion to the connecting portion is smaller than a distance from an end of the first sub-portion to the connecting portion and a distance from an end of the third sub-portion to the connecting portion. The drain includes a connecting block, a first drain and a second drain disposed in the two recesses respectively, and at least a portion of the connecting block is disposed between the first and the second drains to connect the first and the second drains.

Thin film transistor and method for manufacturing the same, array substrate and display device

The disclosure discloses an array substrate, a display panel and a display device. The array substrate includes a peripheral circuit area in which a plurality of first wire grooves, a plurality of second wire grooves, a plurality of first lead wires and a plurality of second lead wires are arranged, wherein each first lead wire is arranged corresponding to one of the first wire grooves, and laid out on a bottom and sidewalls of a corresponding first wire groove; and each second lead wire is arranged corresponding to one of the second wire grooves, and a plurality of recesses and protrusions are arranged alternately on a bottom surface of each second wire groove along an extension direction of the each second wire groove, wherein each second lead wire is laid out on surfaces of recesses and protrusions on a bottom surface of a corresponding second wire groove.

Array substrate, display panel and display device

A TFT array substrate, its manufacturing method and a corresponding display device are disclosed. The TFT array substrate, includes a bearing substrate, a gate line and a data line arranged across each other on the bearing substrate, a pixel region defined by the gate line and the data line, and a thin film transistor, a pixel electrode and an active layer disposed in the pixel region. Specifically, a gate of the thin film transistor is connected to the gate line, a source thereof is connected to the data line and a drain thereof is connected to the pixel electrode. Further, an insulating layer is also formed above the source of the thin film transistor, and a drain trench is formed in the insulating layer. In addition, the drain of the thin film transistor is in the drain trench and is connected to the source through the active layer.

TFT array substrate and manufacturing method thereof, display device

A TFT and a method for manufacturing the same, an array substrate and a display device are provided. The TFT includes a first electrode pattern and a second electrode pattern arranged at an identical layer. The first electrode pattern includes a first strip-like portion extending in a first direction, and the second electrode pattern includes a bending portion surrounding a first end of the first strip-like portion. The second electrode pattern further includes a second strip-like portion extending from a first end of the bending portion in the first direction. A channel formation region of the TFT includes a region between the bending portion and the first strip-like portion, and a region between the second strip-like portion and the first strip-like portion.

It is provided a grayscale voltage debugging method for debugging a display device including a white subpixel, including a first step of, in a state where the white subpixel is disenabled and subpixels in other colors are enabled, adjusting a respective to-be-adjusted grayscale voltage applied to each of the subpixels in other colors, so that a first actually-measured Gamma curve corresponding to the respective adjusted grayscale voltage is located within an acceptable range of a standard Gamma curve, and a second step of, in a state where the white subpixel and the subpixels in other colors are all enabled, acquiring a second actually-measured Gamma curve and in the case that the second actually-measured Gamma curve is not located within the acceptable range, changing the respective adjusted grayscale voltage to obtain a new respective to-be-adjusted grayscale voltage, and returning to the first step.

Grayscale voltage debugging method and device, and display device

The present application discloses a display panel having a plurality of gate lines and a gate driving circuit for driving the plurality of gate lines, the gate driving circuit including a plurality of first cascaded shift register units and a plurality of second cascaded shift register units for applying gate scanning signals to gate lines connected thereto. The display panel includes a first pair of first cascaded shift register unit and second cascaded shift register unit; a second pair of first cascaded shift register unit and second cascaded shift register unit; the second pair adjacent to the first pair; the first cascaded shift register unit in the first pair is electrically coupled to the second cascaded shift register unit in the second pair; and the second cascaded shift register unit in the first pair is electrically coupled to the first cascaded shift register unit in the second pair; a first group of gate lines connecting the first pair of first cascaded shift register unit and second cascaded shift register unit; and a second group of gate lines connecting the first cascaded shift register unit in the first pair and the first cascaded shift register unit in the second pair. The gate driving circuit includes a first column of cascaded shift register units and a second column of cascaded shift register units, the first column and the second column having a same number of cascaded shift register units; the first cascaded shift register unit in the first pair is an odd numbered cascaded shift register unit in the first column, the second cascaded shift register unit in the first pair is an odd numbered cascaded shift register unit in the second column, the first cascaded shift register unit in the second pair is an even numbered cascaded shift register unit in the second column, and the second cascaded shift register unit in the second pair is an even numbered cascaded shift register unit in the first column.

Gate driving circuit, display panel and display apparatus having the same, and driving method thereof

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Beijing, China

Keke Gu