Ningbo University

Keji Zhou

Pengjun Wang

Yuejun Zhang

Huihong Zhang

Daohui Gong

Weiwei Chen

A static memory cell capable of balancing bit line leakage currents is characterized by including a 1PMOS transistor, a 2PMOS transistor, a 1NMOS transistor, a 2NMOS transistor, a 3NMOS transistor, a 4NMOS transistor, a 5NMOS transistor, a 6NMOS transistor, a 7NMOS transistor, an 8NMOS transistor, a write word line, a read word line, a read bit line, an inverted read bit line, a write bit line and an inverted write bit line. The 1NMOS transistor, the 2NMOS transistor, the 3NMOS transistor and the 4NMOS transistor are all normal threshold NMOS transistors. The 1PMOS transistor and the 2PMOS transistor are both low threshold PMOS transistors. The 5NMOS transistor, the 6NMOS transistor, the 7NMOS transistor and the 8NMOS transistor are all low threshold NMOS transistors. The static memory cell has the advantages of high read operation speed, low power consumption and high stability under low operating voltage conditions.

Static memory cell capable of balancing bit line leakage currents

The present invention discloses a replica bit-line circuit, comprising a replica unit, the 1inverter, the 2inverter, the 3inverter, the 4inverter, the 5inverter, the 6inverter, the 7inverter, the 8inverter, the 9inverter, the 1NAND gate, the 2NAND gate, the 3NAND gate, the 1NOR gate, the 2NOR gate and the 1PMOS tube; the 2NOR gate is provided with the 1input terminal, the 2input terminal, a set terminal and an output terminal; advantages of the present invention are stated as follows: It can inhibit feedback oscillation incurred by replica bit-line and replica wordline signal to obtain accurate wordline control signal; it can save switching power consumption of memory array by 53.7% under the power voltage of 1.2V.

Replica bit-line control circuit

The present invention discloses a static RAM for defensive differential power consumption analysis, comprising a replica bit-line circuit, a decoder, an address latch circuit, a clock circuit, n-bit memory arrays, n-bit data selectors, n-bit input circuit and n-bit output circuits; the output circuits comprises a sensitivity amplifier and a data latch circuit; the 1st PMOS tube, the 2nd PMOS tube, the 3rd PMOS tube, the 4th PMOS tube, the 5th PMOS tube, the 6th PMOS tube, the 7th PMOS tube, the 1st NMOS tube, the 2nd NMOS tube, the 3rd NMOS tube, the 4th NMOS tube and the 5th NMOS tube constitute the sensitivity amplifier; two NOR gates, the 8th PMOS tube, the 9th PMOS tube, the 10th PMOS tube, the 11th PMOS tube, the 6th NMOS tube, the 7th NMOS tube, the 8th NMOS tube, the 9th NMOS tube and the 10th NMOS tube constitute the data latch circuit; the present invention is characterized in that energy consumption in each working cycle is basically identical, which is provided with higher capability in defense of differential power analysis.

Growing community of inventors

Zhejiang, China

Keji Zhou