Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Keizo Sumida

Nobuo Higaki

Toru Morikawa

Yoshiteru Mino

Yasunori Yamamoto

Akira Miyoshi

Tamotsu Nishiyama

Jiro Miyake

Kazuki Ninomiya

Miki Urano

Hidenori Nanki

Yoshinori Tokimoto

Junichi Terai

A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction 'MCSST Dis decoded, the sum-product result registeroutputs its held value to the path PThe comparatorcompares the magnitude of the held value of the sum-product result registerwith the coded 32-bit integer '0x0000_00FF'. The polarity judging unitjudges whether the eighth bit of the value held by the sum-product result registeris &#x201c;ON'. The multiplexeroutputs one of the maximum value &#x201c;0x0000_00FF&#x201d; generated by the constant generatorthe zero value &#x201c;0x0000_0000&#x201d; generated by the zero generatorand the held value of the sum-product result registerto the data bus

Processor which can favorably execute a rounding process composed of positive conversion and saturated calculation processing

A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction 'MCSST D' is decoded, the sum-product result registeroutputs its held value to the path P. The comparatorcompares the magnitude of the held value of the sum-product result registerwith the coded 32-bit integer '0x0000_00FF'. The polarity judging unitjudges whether the eighth bit of the value held by the sum-product result registeris &#x201c;ON&#x201d;. The multiplexeroutputs one of the maximum value &#x201c;0x0000_00FF&#x201d; generated by the constant generator, the zero value &#x201c;0x0000_0000&#x201d; generated by the zero generator, and the held value of the sum-product result registerto the data bus

After power activation, a transfererdetects a bootstrap programhaving a first error check codeassigned thereto and being stored in a first storage device, subjects the bootstrap programto an error detection/correction process, and transfers the bootstrap programto the second storage device. If the transfer is properly completed, by executing the bootstrap programon the second storage device, the CPUperforms an error detection/correction process for a main programhaving a second error check codeassigned thereto, and transfers the main programto a third storage device, after which the CPU's control branches out to the main programon the third storage device. As a result, system boot can be performed without employing a NOR type flash memory.

Information processing apparatus for performing a system boot by using programs stored in a non-volatile storage device

An information processing device is provided in which a valid initial program is transferred to a RAM while avoiding a invalid block which is present in a low reliable storage device, such as a NAND-type flash memory or the like. A management information storing sectionstores management informationindicating a position of a invalid block in a first storage deviceWhen an information processing deviceis powered on, a transfer determination sectionis controlled to read a BSPfrom a valid block of a first storage devicebased on the management informationand transfer the BSPto a second storage deviceThereby, it is possible to avoid reading of a invalid block present in the first storage device

Information processing device and information processing method

A memory control apparatus is capable of surely becoming consistent with an external memory while avoiding a deterioration in access efficiency to the external memory. The memory control apparatus includes: a data buffer and an address buffer which respectively store data and addresses related to past access requests from a first master; a first comparison unit which compares a new address with the address of the address buffer upon receiving the new address; a buffer control unit which performs one of issuing an access request to an external memory I/F or outputting the data in the data buffer to the first master, depending on the comparison result; a specific access detection unit which disables the contents of the data buffer irrespective of the comparison result.

Memory control apparatus

Information processing apparatus for performing a system boot by using programs stored in a non-voltile storage device

A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction &ldquo;MCSST D,&rdquo; is decoded, the sum-product result register,outputs its held value to the path P,The comparator,compares the magnitude of the held value of the sum-product result register,with the coded 32-bit integer &ldquo;0x0000_00FF&rdquo;. The polarity judging unit,judges whether the eighth bit of the value held by the sum-product result register,is &ldquo;ON&rdquo;. The multiplexer,outputs one of the maximum value &ldquo;0x0000_00FF&rdquo; generated by the constant generator,the zero value &ldquo;0x0000_0000&rdquo; generated by the zero generator,and the held value of the sum-product result register,to the data bus

A processor which executes positive conversion processing, which converts coded data into uncoded data, and saturation calculation processing, which rounds a value to an appropriate number of bits, at high speed. When a positive conversion saturation calculation instruction 'MCSST D1' is decoded, the sum-product result register 6 outputs its held value to the path P1. The comparator 22 compares the magnitude of the held value of the sum-product result register 6 with the coded 32-bit integer '0x0000.sub.-- 00FF'. The polarity judging unit 23 judges whether the eighth bit of the value held by the sum-product result register 6 is 'ON'. The multiplexer 24 outputs one of the maximum value '0x0000.sub.-- 00FF' generated by the constant generator 21, the zero value '0x0000.sub.-- 0000' generated by the zero generator 25, and the held value of the sum-product result register 6 to the data bus 18.

Processor which can favorably execute a rounding process composed of

A start signal is generated which selects, from among a plurality of sub-periods resulting from division of one cycle period of an external clock signal and each having a length equivalent to one cycle period of an internal clock signal, a sub-period at a corresponding position to a setup time of an external device. When the start signal is generated after a CPU (central processing unit) issues a transmission request signal, there is made a transition to a transmission state. An address signal to the external device is held until data transmission starts between the CPU and the external device in synchronization with the external clock signal in the transmission state.

Data processor

An improved signal processor is disclosed which is suitable for convergence processing of images that achieves parallel processing with a smaller bus structure. An arithmetic array is provided which is formed of ten arithmetic cells capable of concurrently operating. Each arithmetic cell is specified by a denotation of E�(column number),y(row number)! where the column number x is 1.ltoreq.x.ltoreq.4 and the row number y is x.ltoreq.y.ltoreq.4. Each arithmetic cell has a multiplier and an adder for multiply-add operation. An arithmetic cell, specified by E�x,y! where 2.ltoreq.x.ltoreq.4 and x.ltoreq.y.ltoreq.4, receives data from an E�x-1,y! arithmetic cell via a direct bus as well as from an E�x-1,y-1! arithmetic cell via an oblique bus. For example, when pixel data items as to four pixels horizontally arranged in an image are fed to the four arithmetic cells in the first column, the arithmetic cell in the fourth column provides a 4-tap horizontal filter operation result.

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Hirakata, Japan

Keizo Sumida