Sharp Kabushiki Kaisha Corporation

Sharp Laboratories of America, Inc

Keizo Sakiyama

Kenichi Tanaka

Yoshimitsu Yamauchi

Shigeo Onishi

Jun Kudo

Hiroshi Ishihara

Sheng Teng Hsu

Kazuya Ishihara

Yasuyuki Itoh

Seiichi Yokoyama

Yoshi Ono

Katsuji Iguchi

Nobuyoshi Awaya

Toshiyuki Okumura

Wei Gao

Shinichi Sato

John F Conley, Jr

Katsumi Fukumoto

Masayuki Fujimoto

Toshio Mimoto

Yasuyuki Ito

Toshimasa Suzuki

Shigeo Ohnishi

Makoto Tanigawa

Akitsu Ayukawa

Kohji Inoue

Satoshi Saito

Masanori Yoshimi

Jinke Tang

Hidehisa Tateoka

Tatsushi Yusuki

Yuji Nishi

Hitoshi Urashima

Osamu Nishio

A method is provided for forming an electroluminescent device. The method comprises: providing a type IV semiconductor material substrate; forming a p+/n+ junction in the substrate, typically a plurality of interleaved p+/n+ junctions are formed; and, forming an electroluminescent layer overlying the p+/n+ junction(s) in the substrate. The type IV semiconductor material substrate can be Si, C, Ge, SiGe, or SiC. For example, the substrate can be Si on insulator (SOI), bulk Si, Si on glass, or Si on plastic. The electroluminescent layer can be a material such as nanocrystalline Si, nanocrystalline Ge, fluorescent polymers, or type II&#x2013;VI materials such as ZnO, ZnS, ZnSe, CdSe, and CdS. In some aspect, the method further comprises forming an insulator film interposed between the substrate and the electroluminescent layer. In another aspect, the method comprises forming a conductive electrode overlying the electroluminescent layer.

Electroluminescent device

There is provided an EPIR device which is excellent in mass productivity and high in practical utility. The EPIR device includes a lower electrode layer, a CMR thin film layer and an upper electrode layer which are laminated in this order on any of various substrates. A Pt polycrystal thin filmforming the lower electrode layer includes columnar Pt crystal grainsA,B,C, . . . and over 90% of these crystal grains is oriented to a (1 1 1) face. Columnar PCMO crystal grain groupsA,B,C, . . . are respectively locally grown epitaxially on the respective outermost surfaces of the Pt crystal grainsA,B,C, . . . . Then, the crystal faces of the crystal grains included in the PCMO crystal grain groupsA,B,C, . . . and vertical in the substrate surface normal direction are any one of (1 0 0), (1 1 0)and (1 1 1)planes.

EPIR device and semiconductor devices utilizing the same

A spin transistor employing the ferromagnetic semiconductor/semiconductor heterojunction is disclosed. The ferromagnetic semiconductor layers form heterojunctions directly on the source and drain of a regular field effect transistor. Using room temperature ferromagnetic semiconductor materials such as iron doped titanium oxide, the spin transistor can have improved spin injection efficiency due to the conductance matching of the ferromagnetic semiconductor with the semiconductor source and drain. The spin transistor further comprises writing plates to modify the magnetic polarization of the ferromagnetic layers to provide memory states. The spin transistor can be used as a memory cell in a magnetic random access memory with potentially large memory signal by utilizing the magnetic moment induced resistivity change.

Spin transistor magnetic random access memory device

A method is provided for forming silicided source/drain electrodes in active devices in which the electrodes have very thin junction regions. In the process, adjacent active areas are separated by isolation regions, typically by LOCOS isolation, trench isolation or SOI/SIMOX isolation. A contact material, preferably silicide, is deposited over the wafer and the underling structures, including gate and interconnect electrodes. The silicide is then planed away using CMP, or another suitable planing process, to a height approximate the height of the highest structure. The silicide is then electrically isolated from the electrodes, using an etch back process, or other suitable process, to lower the silicide to a height below the height of the gate or interconnect electrode. The wafer is then patterned and etched to remove unwanted silicide. The remaining silicide typically forms silicided source regions and silicided drain regions that extend over a portion of the adjacent isolation regions such that the silicided source/drain regions are larger than the underlying source/drain regions to provide a larger contact area.

Raised silicide source/drain MOS transistors having enlarged source/drain contact regions and method

In a semiconductor memory device, a tantalum silicon nitride film or hafnium silicon nitride film is provided, as a diffusion barrier layer, between a polysilicon plug which electrically connects a source/drain region to a lower platinum electrode of a capacitor, formed on a silicon substrate, and the lower platinum electrode. The tantalum silicon nitride film has a composition of Ta.sub.X Si.sub.1-X N.sub.Y wherein 0.75 .ltoreq.X.ltoreq.0.95 and 1.0 .ltoreq.Y.ltoreq.1.1. The hafnium silicon nitride film has a composition of Hf.sub.X Si.sub.1-X N.sub.Y wherein 0.2&lt;X&lt;1.0 and 0&lt;Y&lt;1.0.

Semiconductor memory device with amorphous diffusion barrier between

In the nonvolatile semiconductor memory including a memory cell array having memory cells arranged in a matrix of the present invention, the memory cell array includes: a semiconductor substrate; a tunnel oxide film formed on the semiconductor substrate; floating gates formed on the tunnel oxide film; first insulating films formed on the floating gates; and control gates formed on the first insulating films, wherein each of the floating gates includes a first polysilicon film and second polysilicon films, the second polysilicon films being formed on both sides of the first polysilicon film, second insulating films are formed on the tunnel oxide film between the first polysilicon films, the second insulating films having a predetermined thickness which is thinner than that of the first polysilicon films, and the second polysilicon films are formed on the second insulating films.

Nonvolatile semiconductor memory with a floating gate that has a bottom

A method for etching a ferroelectric film made of a compound containing lead of the present invention, includes the steps of: forming an insulating film, metal films, and a ferroelectric film on a substrate in this order; forming an etching resistant film on the ferroelectric film, followed by patterning; and etching the ferroelectric film with a mixed gas containing an inert gas and a halogen gas or a halogenated gas as an etching gas, using the patterned etching resistant film as an etching mask.

Method for etching ferroelectric film

A method for etching a Pt film of the present invention includes the steps of: forming an etching resistant film on a Pt film, followed by patterning; etching the Pt film by using as an etching mask the etching resistant film and by using, as an etching gas, a mixed gas containing oxygen gas and chlorine gas or chloride gas, during which layers made of PtCl.sub.x O.sub.y or a mixture containing PtCl.sub.x and PtO.sub.y are formed on side walls of the etching resistant film and the Pt film; and removing the layers made of PtCl.sub.x O.sub.y or the mixture containing PtCl.sub.x and PtO.sub.y with an acid by wet etching after the etching step.

Method for etching PT film

A method for a wiring layer on a semiconductor substrate wherein a contact hole for a wiring layer is formed by laminating a lower insulating layer and an etching barrier layer on the semiconductor substrate providing electrodes via a gate insulating film, forming a hole in the etching barrier layer using a first mask pattern having a hole pattern in which a diameter of the hole thereof is larger than that of the contact hole to be formed, laminating an upper insulating layer and a second mask pattern having a hole pattern in which a diameter of the hole thereof is substantially the same as that of the contact hole, subjecting the lower and upper insulating layers and the gate insulating film to an isotropic etching and an anisotropic etching, utilizing the second mask pattern, thereby forming a contact hole having no exposure of the etching barrier layer at the side of wall of the contact hole.

Method for forming a wiring layer

Random access memory includes a pair of metal oxide semiconductor (MOS) transistors which are connected to each other by a common impurity diffusion region, and a capacitor which is formed of ferroelectric film acting as a capacitor layer and is connected to the impurity diffusion region, one of the pair of MOS transistors being connected to a bit line and a word line.

Non-volatile random access memory with ferroelectric capacitor

A non-volatile random access memory comprising a plurality of unit cells each of which includes; a transistor composed of source/drain and gate electrodes, a ferroelectric capacitor connected to either of the source/drain electrodes and a high load device connected to both of the ferroelectric capacitor and the source/drain electrodes being connected to the ferroelectric capacitor.

Non-volatile random access memory having a high load device

A nonvolatile random access memory comprising a nonvolatile random access memory unit having on a substrate an EEPROM having a tunnel oxide film and a floating gate, and a DRAM linked to the EEPROM, a thermal oxide film being selectively formed between the EEPROM and another EEPROM adjacent thereto, the tunnel regions of the respective EEPROMs being provided as self-aligned with the respective ends of the thermal oxide film and positioned at the respective ends of an impurity ion implantation pattern for use in forming a source region of the EEPROMs.

Process for fabricating nonvolatile random access memory having a tunnel

A non-volatile memory includes a single transistor having a semiconductor substrate, source and drain diffusion layers formed on a surface of the semiconductor substrate, and a gate electrode provided on the semiconductor substrate with a gate insulating film interposed between them. The non-volatile memory further includes a programmable insulating film provided in self-alignment between the gate electrode and at least one of the source and drain diffusion layers and the programmable insulating film is broken down by a voltage applied to the gate electrode so as to execute programming.

Non-volatile memory

A dynamic random access memory includes a plurality of DRAM cell units having a bit contact region and DRAM cells formed on an active region, wherein the DRAM cells each comprised of a transistor and a capacitor connected to the transistor are arranged symmetrically to the right and left sides in a bit contact connected with the active region to form the DRAM cell unit; and the DRAM cell units are arranged with a prescribed pitch in the direction of X and arranged in the direction of Y shifted with one third of the pitch toward the direction of X.

Dynamic random access memory

A semiconductor memory device which comprises unit memory cells each including two transistors each having a source/drain region and a gate electrode and one capacitor having a capacitor dielectric film, an upper electrode and a lower electrode, the gate electrode of each transistor being connected to a common word line, one source/drain region of each transistor being connected to a bit line and a reversed bit line respectively and the other source/drain region being connected to the upper electrode and the lower electrode respectively, and the bit line, the reversed bit line and the word line being disposed under the lower electrode of the capacitor.

Growing community of inventors

Kashihara, Japan

Keizo Sakiyama